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digital power factor correction controller with accurate ac power metering data sheet ADP1047/adp1048 features flexible digital power factor correction (pfc) controller single phase operation ( ADP1047 ); interleaved and bridgeless operation ( adp1048 ) true rms ac power metering enhanced dynamic response optimized light load efficiency performance output voltage adjustment frequency reduction inrush current control switching frequency spread spectrum for improved emi external frequency synchronization pmbus compliant programmable ac line fault detection and protection programmable output fault detection and protection extensive fault protection for high reliability systems frequency range from 30 khz to 400 khz 8 kb eeprom programming via easy-to-use graphical user interface (gui) applications ac/dc power supplies for applications computing server and storage network and communication infrastructure industrial and medical general description the ADP1047 / adp1048 are digital power factor correction (pfc) controllers that provide accurate input power metering capability and inrush current control for ac/dc systems. the ADP1047 is designed for single phase pfc applications; the adp1048 is designed especially for interleaved and bridgeless pfc applications. the digital pfc function is based on a conventional boost pfc with multiplication of the output voltage feedback combined with the input current and voltage to provide optimum harmonic correction and power factor for ac/dc systems. all signals are converted into the digital domain to provide maximum flexibility; all key parameters can be reported and adjusted via the pmbus? interface. the ADP1047 / adp1048 allow users to optimize system performance, maximize efficiency across the load range, and reduce design time to market. the ADP1047 / adp1048 provide accurate rms measurement of input voltage, current, and power. this information can be reported to the microcontroller of the power supply via the pmbus interface. typical applications circuit 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 res rtd add sync inrush scl sda vac vfb ovp nc ilim pgnd agnd cs? 9 10 11 12 16 15 14 13 pson dgnd cs+ pwm2 vcore pwm ac_ok pgood vdd ADP1047 v rec relay v out bulk capacito r 3.3v pmbus ac input 09696-101 figure 1. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved.
ADP1047/adp1048 data sheet rev. 0 | page 2 of 84 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? typical applications circuit ............................................................ 1 ? revision history ............................................................................... 4 ? specifications ..................................................................................... 6 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configurations and function descriptions ......................... 10 ? functional block diagrams ........................................................... 11 ? controller architecture ................................................................. 12 ? current sense .............................................................................. 12 ? rms input overcurrent protection ......................................... 12 ? fast overcurrent protection (ilim pin) ................................. 12 ? current balancing (ibal pin, adp1048 only) ..................... 14 ? voltage sense ............................................................................... 14 ? overvoltage protection .............................................................. 15 ? power factor correction control loop ...................................... 17 ? digital compensation filters .................................................... 17 ? pulse-width modulation ........................................................... 18 ? duty cycle minimum/maximum limits ................................ 18 ? auxiliary pwm output (ADP1047 only) .............................. 18 ? switching frequency programming ........................................ 19 ? line fault protections and soft start sequencing ...................... 20 ? pson operation ........................................................................ 20 ? ac line detection ...................................................................... 20 ? soft start procedure ................................................................... 22 ? line fault protections ................................................................ 22 ? advanced input power metering.................................................. 24 ? power supply system and fault monitoring ............................... 25 ? flag conventions ........................................................................ 25 ? manufacturer-specific flags ..................................................... 25 ? standard pmbus flags ............................................................... 26 ? pmbus fault flag response ...................................................... 27 ? manufacturer-specific flag response ..................................... 28 ? monitoring functions ................................................................ 29 ? first error fault .......................................................................... 29 ? overtemperature protection (otp) ........................................ 29 ? ac_ok and pgood signals ................................................... 29 ? advanced features ......................................................................... 30 ? frequency dithering (spread spectrum) ................................ 30 ? pwm frequency synchronization ........................................... 30 ? smart output voltage (load line) .......................................... 30 ? smart switching frequency ...................................................... 31 ? current loop filter for light load .......................................... 31 ? phase shedding (adp1048 only) ............................................ 31 ? current loop feedforward ....................................................... 31 ? bridgeless boost operation (adp1048 only)........................ 32 ? power supply system calibration and trim ............................... 33 ? output voltage (vfb) calibration and trim ......................... 33 ? input voltage (vac) gain and offset trim ............................ 33 ? current sense gain and offset trim ....................................... 33 ? input power gain and offset trim .......................................... 33 ? pmbus digital communication ................................................... 34 ? features ........................................................................................ 34 ? overview ..................................................................................... 34 ? pmbus address .......................................................................... 34 ? data transfer............................................................................... 35 ? general call support ................................................................. 36 ? fast mode .................................................................................... 36 ? fault conditions ......................................................................... 36 ? timeout condition .................................................................... 36 ? data transmission faults .......................................................... 37 ? data content faults ................................................................... 37 ? eeprom ......................................................................................... 38 ? overview ..................................................................................... 38 ? page erase operation ................................................................. 38 ? read operation (byte read and block read) ........................ 38 ? write operation (byte write and block write) ..................... 39 ? eeprom password .................................................................... 39 ? downloading eeprom settings to internal registers ......... 39 ? saving register settings into eeprom .................................. 40 ? eeprom crc checksum ........................................................ 40 ? software gui .................................................................................. 41 ? standard pmbus commands supported by the ADP1047/adp1048 ....................................................................... 42 ? manufacturer-specific pmbus commands ................................ 43 ? detailed register descriptions ..................................................... 45 ? operation register ............................................................... 45 ?
data sheet ADP1047/adp1048 rev. 0 | page 3 of 84 on_off_config register ..................................................... 45 ? clear_faults command ..................................................... 45 ? write_protect register ..................................................... 45 ? restore_default_all command .................................. 45 ? store_user_all command ................................................ 45 ? restore_user_all command .......................................... 46 ? capability register ............................................................... 46 ? vout_mode register ............................................................. 46 ? vout_command register .................................................. 46 ? vout_scale_loop register ............................................... 46 ? vout_scale_monitor register ...................................... 47 ? vin_on register........................................................................ 47 ? vin_off register ...................................................................... 47 ? vout_ov_fault_limit register ...................................... 47 ? vout_ov_fault_response register ............................. 47 ? vout_ov_warn_limit register ...................................... 48 ? vout_uv_warn_limit register ...................................... 48 ? vout_uv_fault_limit register ...................................... 48 ? vout_uv_fault_response register ............................. 49 ? ot_fault_response register ............................................ 49 ? vin_ov_fault_limit register........................................... 50 ? vin_ov_fault_response register .................................. 50 ? vin_uv_warn_limit register ........................................... 51 ? vin_uv_fault_limit register .......................................... 51 ? vin_uv_fault_response register .................................. 52 ? iin_oc_fault_limit register ............................................ 52 ? iin_oc_fault_response register ................................... 53 ? iin_oc_warn_limit register ............................................ 53 ? pin_op_warn_limit register ............................................ 54 ? status_byte register ............................................................ 54 ? status_word register ......................................................... 54 ? status_vout register ........................................................... 55 ? status_input register ......................................................... 55 ? status_temperature register ........................................ 55 ? read_vin register ................................................................... 55 ? read_iin register .................................................................... 55 ? read_vout register .............................................................. 56 ? read_pin register ................................................................... 56 ? pmbus_revision register .................................................... 56 ? mfr_id register ........................................................................ 56 ? mfr_model register .............................................................. 56 ? mfr_revision register ......................................................... 56 ? eeprom_data_00 through eeprom_data_15 commands ................................................................................... 56 ? eeprom_crc_chksum register ....................................... 57 ? eeprom_num_rd_bytes register ................................... 57 ? eeprom_addr_offset register ....................................... 57 ? eeprom_page_erase register ........................................... 57 ? eeprom_password register .............................................. 57 ? trim_password register .................................................... 57 ? eeprom_info command ..................................................... 57 ? cs_fast_ocp_response register ..................................... 58 ? ovp_fast_ovp_response register ................................. 58 ? olp_response register ......................................................... 58 ? vdd3p3_response register ................................................. 59 ? vcore_response register ................................................... 59 ? pgood_ac_ok_debounce_set register ..................... 59 ? pson_set register ................................................................... 60 ? flag_fault_id register ....................................................... 60 ? softstart_flags_blank1 register ............................... 61 ? softstart_flags_blank2 register ............................... 61 ? pgood_flags_list register ............................................... 61 ? ac_ok_flags_list register ................................................ 61 ? pwm and pwm2 timing registers ........................................ 62 ? pwm_set register .................................................................... 63 ? pwm_limit register ............................................................... 63 ? rtd adc offset trim setting (msb) register ...................... 63 ? rtd adc offset trim setting (lsb) register ....................... 63 ? rtd adc gain trim setting register .................................... 64 ? ot_fault_limit register ..................................................... 64 ? ot_warn_limit register ..................................................... 64 ? switching frequency setting register ...................................... 65 ? low power switching frequency setting register ................. 66 ? frequency dithering set register ............................................. 67 ? frequency synchronization set register ................................. 68 ? voltage loop filter gain register ............................................. 68 ? voltage loop filter zero register ............................................. 68 ? fast voltage loop filter gain register ..................................... 68 ? fast voltage loop filter zero register ..................................... 68 ? fast voltage loop enable register ............................................ 68 ? vac_threshold_set register .......................................... 69 ? vac_threshold_read register ...................................... 69 ?
ADP1047/adp1048 data sheet rev. 0 | page 4 of 84 min_ac_period_set register ........................................... 69 ? max_ac_period_set register .......................................... 69 ? current loop filter gain for low line input register ......... 70 ? current loop filter zero for low line input register ......... 70 ? current loop filter gain for high line input register ........ 70 ? current loop filter zero for high line input register ........ 70 ? soft start set register ................................................................. 70 ? inrush set register ..................................................................... 71 ? fast_ovp_fault_rise register ......................................... 71 ? fast_ovp_fault_fall register ........................................ 71 ? fast ovp debounce time setting register ......................... 71 ? low power mode operation threshold register .................. 72 ? power metering offset trim for low line input register .... 72 ? power metering gain trim for low line input register ...... 72 ? high line limit register ........................................................... 72 ? low line limit register ............................................................ 72 ? ilim_trim register ................................................................. 72 ? voltage loop output register .................................................. 72 ? exponent register ...................................................................... 73 ? read update rate register ........................................................ 73 ? vin scale monitor register ...................................................... 73 ? iin_gsense register ............................................................... 73 ? cs fast ocp blank register ..................................................... 74 ? cs fast ocp setting register ................................................... 74 ? temperature hysteresis register .............................................. 74 ? vac adc gain trim register ................................................. 75 ? vfb adc gain trim register .................................................. 75 ? cs adc gain trim for 500 mv range register .................... 75 ? ibal gain register (adp1048 only) ..................................... 75 ? smart vout low power threshold (p1) register ............... 75 ? smart vout high power threshold (p2) register .............. 75 ? smart vout low line (vol1) register ................................ 76 ? smart vout low line (vol2) register ................................ 76 ? smart vout high line (voh1) register ............................. 76 ? smart vout high line (voh2) register ............................. 76 ? smart vout upper limit (voh) register ........................... 76 ? smart vout super high line register .................................. 76 ? sync delay register ................................................................. 76 ? smart_vout_super_high_line_hys register ........ 77 ? power_hys register .............................................................. 77 ? advanced feature enable register ........................................... 77 ? vout_ov_fault_hys register ......................................... 77 ? vin_uv_fault_hys register .............................................. 77 ? vac adc offset trim register ............................................... 78 ? cs adc offset trim for 500 mv range register ................. 78 ? cs adc gain trim for high (750 mv) range register....... 78 ? cs adc offset trim for high (750 mv) range register .... 78 ? latched flag registers ............................................................... 78 ? pwm value register .................................................................. 79 ? vac_line_period register ................................................. 79 ? read temperature adc register ............................................. 79 ? power metering offset trim for high line input register .. 79 ? power metering gain trim for high line input register .... 80 ? current loop filter gain for low line input and light load register .............................................................................. 80 ? current loop filter zero for low line input and light load register .............................................................................. 80 ? current loop filter gain for high line input and light load register .............................................................................. 80 ? current loop filter zero for high line input and light load register .............................................................................. 80 ? smart vout power reading register .................................... 80 ? ibal configuration register (adp1048 only) ..................... 81 ? debug flag registers .................................................................. 81 ? outline dimensions ....................................................................... 83 ? ordering guide .......................................................................... 83 ? revision history 9/11revision 0: initial version
data sheet ADP1047/adp1048 rev. 0 | page 5 of 84 the combination of a flexible, digitally controlled pfc engine and accurate input power metering facilitates the adoption of intelligent power management systems that are capable of making decisions to improve end-user system efficiency. the device supports additional efficiency improvements through programmable frequency reduction at light load and the capability to reduce the output voltage at light load. the ADP1047 / adp1048 provide enhanced integrated features and functions; the inrush current and soft start control functions provide significant component count reduction with easy design optimization. the devices are designed for high reliability, redundant power supply applications and have extensive and robust protection circuitry: independent overvoltage protection (ovp) and overcurrent protection (ocp), ground continuity monitoring, and ac sensing. internal overtemperature protection (otp) is provided whereby the external temperature can be recorded via an external sensing device. the internal 8 kb eeprom stores all programmed values and allows standalone control without a microcontroller. all parametric reporting and adjustments can be programmed via an easy-to-use gui. no complex programming is required. the ADP1047 / adp1048 operate from a single 3.3 v supply. the devices are available in a 24-lead qsop package that is specified over an ambient temperature range of ?40c to +85c. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 res rtd add sync inrush scl sda vac vfb ovp ibal ilim pgnd agnd cs? 9 10 11 12 16 15 14 13 pson dgnd cs+ pwm2 vcore pwm ac_ok pgood vdd adp1048 v rec relay v out bulk capacito r 3.3v pmbus ac input 09696-102 figure 2. typical interleaved application, adp1048
ADP1047/adp1048 data sheet rev. 0 | page 6 of 84 specifications vdd = 3.3 v, t a = ?40c to +85c, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit power supply operating supply voltage vdd 3.0 3.3 3.6 v supply current i dd normal operation (pson high) and no load on pwm output 17 40 ma supply current for programming i dd_pk during eeprom programming (50 ms) i dd + 8 ma shutdown current i dd_sd 100 a power-on reset power-on reset vdd rising 1.8 3 v undervoltage lockout uvlo vdd falling 2.75 2.85 2.95 v overvoltage lockout ovlo 3.7 3.9 4.1 v vcore pin output voltage range temperature = 25c 2.26 2.45 2.65 v pwm outputs pwm, pwm2 pins output low voltage v pwmol sink current = 10 ma 0.4 v output high voltage v pwmoh source current = 10 ma vdd ? 0.4 v rise time c load = 50 pf 4 ns fall time c load = 50 pf 4 ns vac adc input voltage range 0 1.6 v leakage current 5 a equivalent resolution 11 bits voltage sense measurement accuracy from 2.5% to 97.5% of input voltage range vdd = 3.3 v ?1.3 +1.3 % fsr vdd varies from 3.0 v to 3.6 v ?1.99 +1.99 % fsr vfb adc input voltage range 0 1.6 v equivalent resolution 11 bits voltage sense measurement accuracy from 2.5% to 97.5% of input voltage range vdd = 3.3 v ?1.2 +1.2 % fsr vdd varies from 3.0 v to 3.6 v ?1.72 +1.72 % fsr current sense adc high input voltage range 0 750 mv low input voltage range 0 500 mv equivalent resolution 11 bits current sense measurement accuracy from 0% to 97.5% of input voltage range vdd = 3.3 v ?1.7 +1.7 % fsr vdd varies from 3.0 v to 3.6 v ?2.06 +2.06 % fsr current source 10 k level shifting resistor, v cs+ ? v cs? = 0 v high input 74 a low input 84 a current source resolution 0.03 % rtd pin input voltage range 0 0.8 v current source accuracy 9 10 11 a equivalent resolution 14 bits
data sheet ADP1047/adp1048 rev. 0 | page 7 of 84 parameter symbol test conditions/comments min typ max unit voltage sense measurement accuracy from 2.5% to 97.5% of input voltage range vdd = 3.3 v ?1.52 +1.52 % fsr vdd varies from 3.0 v to 3.6 v ?1.97 +1.97 % fsr ibal pin ( adp1048 only) interleaved operation mode input voltage range 0 0.8 v equivalent resolution 11 bits channel mismatch dc input and acquiring time window on each channel is 526 s ?5 +5 % fsr power meter measurement accuracy from 2.5% to 97.5% of input voltage range vdd = 3.3 v ?2.3 +2.3 % fsr vdd varies from 3.0 v to 3.6 v ?2.75 +2.75 % fsr switching frequency frequency range programmable 30 400 khz accuracy ?3.85 +3.85 % oscillator, clock, and pll oscillator frequency 1.516 1.56 1.62 mhz digital clock frequency 200 mhz pll frequency 200 mhz res pin temperature stability ?120 0 +120 ppm/c pgood, ac_ok pins output low voltage 0.8 v output high voltage 2.0 v fast overcurrent protection fast ocp threshold positive signal 1455 1500 1550 mv negative signal 452 500 523 mv current source accuracy 4.4 % current source resolution 3.2 % propagation delay from threshold trip to pwm disabled 140 ns rms overcurrent protection rms accuracy vdd = 3.3 v ?1.7 +1.7 % propagation delay ac line frequency = 50 hz 12 ms fast overvoltage protection fast ovp threshold fully programmable from 1 v to 1.5 v rising register 0xfe2f, bits[6:0] 1 1.5 v falling register 0xfe30, bits[6:0] 1 1.5 v ovp threshold minimum step 3.9 mv accuracy ?4 +4 lsb propagation delay (latency) does not include blanking/debounce 120 ns blanking time blanking after threshold reprogramming 10 s accurate overvoltage protection accuracy vdd = 3.3 v ?1.2 +1.2 % propagation delay ac line frequency = 50 hz 12 ms open-loop protection vfb error threshold vfb 33 111 242 mv propagation delay 200 ns debounce time 10 s common-mode input range ?0.2 +1.6 v
ADP1047/adp1048 data sheet rev. 0 | page 8 of 84 parameter symbol test conditions/comments min typ max unit sda, scl pins vdd = 3.3 v input low voltage 0.8 v input high voltage 2.2 v output low voltage 0.4 v pull-up current 100 350 a leakage current ?5 +5 a serial bus timing clock frequency 10 100 400 khz glitch immunity t sw 50 ns bus free time t buf 1.3 s start condition hold time t hd;sta 0.6 s start condition setup time t su;sta 0.6 s stop condition setup time t su;sto 0.6 s data hold time t hd;dat 300 ns data setup time t su;dat 100 ns scl low timeout t timeout 25 35 ms scl low time t low 1.3 s scl high time t high 0.6 s clock low extend time t low;sext 25 ms scl, sda rise time t r 20 300 ns scl, sda fall time t f 20 300 ns eeprom reliability endurance 10,000 cycles data retention temperature = 85c 20 years
data sheet ADP1047/adp1048 rev. 0 | page 9 of 84 absolute maximum ratings thermal resistance table 2. parameter rating supply voltage (continuous), vdd 3.8 v digital core supply voltage, vcore 2.7 v digital pins ?0.3 v to vdd + 0.3 v analog pins ?0.3 v to vdd + 0.3 v agnd to dgnd ?0.3 v to +0.3 v operating temperature range ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c peak solder reflow temperature snpb assemblies (10 sec to 30 sec) 240c rohs-compliant assemblies (20 sec to 40 sec) 260c ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 24-lead qsop (rq-24) 44.4 6.4 c/w esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADP1047/adp1048 data sheet rev. 0 | page 10 of 84 09696-003 pin configurations and function descriptions 1 2 3 4 5 6 7 8 nc = no connect. do not connect to this pin. 24 23 22 21 20 19 18 17 res rtd add sync inrush scl sda vac vfb ovp nc ilim pgnd agnd cs? 9 10 11 12 16 15 dgnd cs+ ac_ok pgood vdd ADP1047 top view (not to scale) 14 13 pson pwm2 vcore pwm 09696-004 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 res rtd add sync inrush scl sda vac vfb ovp ibal ilim pgnd agnd cs? 9 10 11 12 16 15 14 13 pson dgnd cs+ pwm2 vcore pwm ac_ok pgood vdd adp1048 top view (not to scale) figure 3. ADP1047 pin configuration figure 4. adp1048 pin configuration table 4. pin function descriptions pin no. mnemonic description 1 agnd analog ground. agnd should be connected directly to dgnd. 2 vac input line voltage sense. the vac signal is referred to pgnd. 3 vfb feedback voltage sense. the vfb signal is referred to pgnd. vfb is the feedback signal for pfc power circuit regulation. it is used as the analog voltage input to the vfb adc. 4 ovp overvoltage protection. the ovp signal is referred to pg nd. this signal is used for re dundant overvoltage protection. 5 pgnd power ground. pgnd is the connection for the ground line of the power rail. there should be a low impedance path between pgnd and agnd. 6 ilim fast current limiting. this pin is referred to pgnd. 7 nc/ibal ADP1047 : no connect. do not connect to this pin. adp1048 : current balancing input for interleaved operation. the ibal input is referred to pgnd. 8 cs? differential current sense negative input. the cs? sign al is used for current me asurement, monitoring, and protection. a 0.1%, 10 k resistor must be used to connect to this circuit. 9 cs+ differential current sense positive input. the cs+ sign al is used for current measurement, monitoring, and protection. a 0.1%, 10 k resistor must be used to connect to this circuit. 10 dgnd digital ground. dgnd should be connected directly to agnd. 11 pson power supply enable signal. the pson signal is used to enable/disable the pfc controller. the pson signal is referred to dgnd. 12 vcore output of 2.5 v regulator. connect a 100 nf capacitor from vcore to dgnd. 13 pwm pwm output for pfc regulation. the pwm signal is referred to agnd. 14 pwm2 auxiliary pwm output ( ADP1047 ) or interleaved pwm output ( adp1048 ). the pwm2 signal is referred to agnd. 15 ac_ok open-drain output. user-configurable signal from a co mbination of flags. the ac_ok signal is referred to agnd. 16 pgood open-drain output. user-configurable signal from a co mbination of flags. the pgood signal is referred to agnd. 17 inrush inrush current control signal to an external in rush driver. this open-drain output is referred to agnd. 18 sync allows parallel pfc controllers to synchronize to reduce interference. this pin is referred to dgnd. 19 scl i 2 c serial clock input. the scl signal is referred to dgnd. 20 sda i 2 c serial data input and output (open-drain). the sda signal is referred to dgnd. 21 add address select input. connect a resistor from add to agnd (see the pmbus address section). 22 rtd thermistor input. a thermistor is placed from rtd to agnd. the rtd signal is referred to agnd. 23 res internal voltage reference. connect a 0.1%, 50 k resistor from res to agnd. 24 vdd positive supply input. the range is from 3.0 v to 3.6 v. the vdd signal is referred to agnd.
data sheet ADP1047/adp1048 rev. 0 | page 11 of 84 functional block diagrams adc dac adc adc adc osc cs ocp vac vfb olp ovp + ? 8kb eeprom i 2 c interface digital core pwm engine uvlo ldo vref ADP1047 pgood ovp v fb pgnd v a c ilim inrush pwm pwm2 vdd vcore res cs+cs? ac_ok sync pson scl sda dgnd agnd rtd add 09696-001 pgnd figure 5. ADP1047 functional block diagram osc 8kb eeprom i 2 c interface digital core pwm engine uvlo ldo vref adp1048 pgood inrush pwm pwm2 vdd vcore res ac_ok sync pson scl sda dgnd 09696-002 adc dac adc adc cs ocp vac vfb olp ovp + ? ovp v fb pgnd v a c ilim cs+ adc cs ib a l pgnd cs? pgnd adc agnd rtd add figure 6. adp1048 functional block diagram
ADP1047/adp1048 data sheet rev. 0 | page 12 of 84 controller architecture the ADP1047 / adp1048 integrate the following functions: the output of the - adc is used for the following purposes: ? power factor correction control loop (see the power factor correction control loop section) ? the output is decimated at the switching frequency for the control loop. the effective number of bits (enob) is >7 when the current loop bandwidth is 10 khz; the enob is >10 when the current loop bandwidth is 1 khz. ? advanced input power metering (see the advanced input power metering section) ? the 11-bit result is calculated and updated at each half line cycle for high accuracy ac line current and input power monitoring and for overcurrent protection (accurate ocp). ? pmbus digital communication (see the pmbus digital communication section) this section describes the internal architecture of the chip. rms input overcurrent protection current sense the ADP1047 / adp1048 provide rms overcurrent protection (ocp). rms ocp (or accurate ocp) is distinct from the instan- taneous pulse-by-pulse fast overcurrent protection and is based on the rms value of the input ac current. current sensing is used for the control, protection, and monitor- ing of the pfc stage. for normal operation, the power factor correction control loop requires inductor current information. the typical implementation uses a sense resistor on the input bus. a combination of two current transformers in series with the power switch and the boost diode can be used to reconstruct the inductor current and minimize losses in the resistive shunt, but, in general, a good quality shunt resistor provides much better accuracy in measuring input current and input power. the measured value is compared to the limit set in the iin_oc_fault_limit register (register 0x5b) at the end of each half cycle of the ac line. if the limit is exceeded, the action programmed in the iin_oc_fault_response register (register 0x5c) is triggered. in addition, an input current warning limit can be programmed in the iin_oc_warn_limit register (register 0x5d). this warning limit has no action attached to it, but it sets flags in the status_byte register (register 0x78, bit 0), the status_word register (register 0x79, bit 13), and the status_input register (register 0x7c, bit 1). the inputs to the current sense adc are differential. a pair of matched current sources is provided to level shift the negative signal across the current sense element in the input range of the current sense adc (see figure 7 ). 09696-005 11-bit adc cs? cs+ 10k? 10k? vdd + ? ADP1047/adp1048 i l fast overcurrent protection (ilim pin) a dedicated current limiting pin (ilim) is provided to protect the part from pulse-by-pulse overcurrent events. when the threshold is crossed, the pwm pulse is terminated. this action is independent of any programming of the fast ocp flag. the next switching cycle resumes normally. additional actions can be programmed (see table 5 ). the ocp comparator on the ilim pin can accept positive or negative signals; the pin is referred to pgnd (power ground) and has programmable level shifting current sources (see table 5 ). these sources can be changed during normal operation to adapt to the level at which the overcurrent protection is triggered. figure 7. current sense configuration the ocp comparator also features programmable blanking and debounce times (see table 5 ). if ocp is triggered, the pwm signal is terminated and operation resumes at the next switch- ing cycle unless a different action is specified for the fast ocp response in register 0xfe00. the current sense can be calibrated digitally to remove any errors due to external components (see the current sense gain and offset trim section). this calibration can be performed in the production environment; the settings are saved in the eeprom of the ADP1047 / adp1048 .
data sheet ADP1047/adp1048 rev. 0 | page 13 of 84 0 9696-006 ocp ilim pgnd 20a to 80a 1500mv vdd ADP1047/adp1048 i m i l ocp ilim pgnd 60a to 120a 500mv vdd ADP1047/adp1048 figure 8. fast overcurrent protection schemes 09696-007 level shifting 10k 120a = 1.2v level shifting 10k 80a = 0.8v 500mv 0mv 1500mv 0mv figure 9. level shifting and threshold for ocp table 5. programmable options fo r fast overcurrent protection parameter values or options comments debounce time 40 ns, 80 ns, 120 ns, 240 ns register 0xfe3d, bits[4:3] blanking time 40 ns, 80 ns, 120 ns, 160 ns, 200 ns, 400 ns, 600 ns, 800 ns blanking from the leading edge; register 0xfe3d, bits[2:0] propagation delay 140 ns typical fixed value; does not include blanking or debounce threshold value and polarity 500 mv (neg ative); 1500 mv (positive) fixed values level shifting current sources 60 a, 80 a, 100 a, 120 a (negative) 20 a, 40 a, 60 a, 80 a (positive) register 0xfe3e, bits[7:5] actions for fast ocp ignore (still terminates the pwm pulse); allow n switching cycles, then shut down and soft start; allow n switching cycles, then shut down and wait for pson signal n = 1, 2, 4, 8; register 0xfe00, bits[7:6]
ADP1047/adp1048 data sheet rev. 0 | page 14 of 84 current balancing (ibal pin, adp1048 only) the adp1048 has a dedicated circuit to maintain current balance in each interleaved phase when operating in interleaved pfc topology. this ensures that each interleaved phase provides equal power regardless of the tolerance of the inductor and the boost switch driving circuitry. the input is through the ibal pin specifically provided for the adp1048 . the current balancing circuit monitors the current flowing in both switches of the interleaved pfc topology and stores this information. it compensates the pwm signals, ensuring equal current flow to balance the current between interleaved phases. several switching cycles are required for the circuit to operate effectively. the current balance settings are programmed in register 0xfe43 and register 0xfe95. 09696-008 ibal pwm pwm2 pgnd adp1048 0 to 180 180 to 360 output of pfc current loop + ? adc adc pwm k figure 10. current balancing (ibal) for the adp1048 voltage sense voltage sensing is used for the control, protection, and monitor- ing of the pfc stage. input and output voltages are sensed using dedicated adcs and references (see figure 11 ). ADP1047/adp1048 09696-009 vac pgnd vfb v out v rec adc 11-bit + ? adc 11-bit + ? + ? dac 7-bit ovp olp ovp figure 11. typical voltage sense configuration the voltage sense can be calibrated digitally to remove any errors due to external components (see the output voltage (vfb) calibration and trim section). this calibration can be performed in the production environment; the settings are saved in the eeprom of the ADP1047 / adp1048 . input voltage sensing (vac pin) the vac pin is used for the monitoring and protection of the rectified power supply input voltage. the sense point on the power rail requires an external resistor divider to bring the signal within the operating input range of the adc (0 v to 1.6 v). this scaled-down signal is fed into a high speed - adc. the output of the - adc goes to the digital filter and is used for the following purposes: ? the output is decimated at the switching frequency for the control loop. the effective number of bits (enob) is >7 when the current loop bandwidth is 10 khz; the enob is >10 when the current loop bandwidth is 1 khz. ? the 11-bit result is calculated and updated at each half line cycle for high accuracy input voltage and power monitoring. output voltage sensing (vfb pin) the vfb pin is used for the control, monitoring, and protection of the output voltage. this voltage is the main feedback loop for the power supply control loop. the sense point on the power rail requires an external resistor divider to bring the signal within the operating input range of the adc (0 v to 1.6 v). this scaled- down signal is fed into a high speed - adc. the output of the - adc goes to the digital filter and is used for the following purposes: ? the 11-bit result is used at each half line cycle for the normal control loop to control the value of the output voltage. ? the 10-bit, 1.5 khz update rate is used for the fast voltage control loop to control the value of the output voltage during large transients. to reduce the current distortion from the output voltage feed- back, a prefilter is implemented before the voltage loop filter. the prefilter detects the zero-crossing point of the input voltage to identify the half input line cycle. the prefilter then performs an averaging function for the sampled vfb signal during this half line cycle. in this way, the fundamental frequency of the output bulk voltage ripple and its harmonics are significantly attenuated.
data sheet ADP1047/adp1048 rev. 0 | page 15 of 84 overvoltage protection the ADP1047 / adp1048 have two ovp circuits: an adc-based comparator and a fast comparator. accurate overvoltage pr otection (vfb pin) overvoltage protection (ovp) is implemented using the infor- mation available on the output of the vfb adc. the information from the vfb adc is averaged over one half the ac line frequency; therefore, the response of this ovp is relatively slow. the threshold for the accurate ovp is fully programmable using the vout_ov_fault_limit register (register 0x40). the programmed value is the dc average voltage. when the accurate ovp threshold is crossed, the accurate ovp flag is set. the response to this flag can be programmed for one of several actions using the vout_ov_fault_response register (register 0x41). if the disable pwm option is selected, a voltage hysteresis can be programmed for the accurate ovp threshold using register 0xfe50. fast overvoltage protection (ovp pin) a fast ovp mode is implemented using a programmable comparator on the ovp pin. fast ovp is used for overvoltage protection of the bulk capacitors and to provide open-loop protection. the sense point on the power rail requires an external resistor divider to match the divider applied to vfb. this separate divider introduces a level of redundancy in sensing the output voltage to improve system reliability. if the voltage divider on the vfb pin is damaged or drifts in value, the ovp pin can still detect an overvoltage condition and take the appropriate programmed action. the fast ovp signal is fed into a comparator with a program- mable threshold to set the trip point for overvoltage. the threshold is set using a dac. table 6. programmable options for fast overvoltage protection (fast ovp) parameter values or options comments debounce time 120 ns, 240 ns, 480 ns, 640 ns minimum duration of pulse to be considered; programmable using register 0xfe31, bits[1:0] blanking time 10 s (fixed) duration of time while the comparator is blanked and the threshold changes from rising to falling propagation delay 120 ns max (fixed) does not include blanking or debounce threshold rising 1 v to 1.5 v programma ble using register 0xfe2f, bits[6:0] threshold falling 1 v to 1.5 v programma ble using register 0xfe30, bits[6:0] actions for fast ovp immediate shutdown and wait for pson; disable pwm until the flag is cleared; shut down and soft start; ignore (do nothing) register 0xfe01, bits[7:6]
ADP1047/adp1048 data sheet rev. 0 | page 16 of 84 figure 12 shows an example of the output voltage and the ovp thresholds set. the rising and falling thresholds, fast_ovp_ fault_rise and fast_ovp_fault_fall, respectively, are used for fast ovp protection. fast_ovp_fault_rise corresponds to ovp up , which is the trip point for overvoltage protection (see figure 13 ). fast_ovp_fault_fall corre- sponds to ovp down , which is the reset point for the fast ovp. when the rising threshold is triggered, the programmed action is applied and the threshold is switched to the programmed fall- ing threshold (if the programmed falling threshold is different from the rising threshold). a blanking time is applied when the thresholds are switched to avoid spurious signals (see the timing diagram in figure 13 ). a programmable debounce time is applied to the ovp signal as well to avoid false triggering. the rising and falling thresholds are programmable from 1 v to 1.5 v (at the ovp pin) using register 0xfe2f and register 0xfe30, respectively. open-loop protection open-loop protection detects differences between the ovp and vfb pins. identical resistor dividers are applied to these pins; therefore, if a voltage difference is present, it means that one or more resistors in the dividers have the wrong values or are not connected. in this case, it is usually recommended that the user shut down the system to prevent damage. the open-loop protection detects a difference in voltage in excess of ~100 mv, which equates to approximately 6.6% of the full-scale range. a debounce time of 10 s is added to avoid false triggering. if filtering capacitors are applied to the ovp and vfb pins, care must be taken to make sure that the time constant difference does not exceed 10 s. adc input range = 1.6v 09696-020 vout_ov_fault_limit = 450v (reg 0x40) fast ovp programming range 1.6v 0.5v 1.0v vout_command = 385v (reg 0x21) vout_uv_fault_limit = 200v (reg 0x44) vout_ov_warn_limit = 420v (reg 0x42) adc full range fast_ovp_fault_rise = 435v (reg 0xfe2f) fast_ovp_fault_fall = 400v (reg 0xfe30) figure 12. output voltage levels 09696-021 ovp up ovp down output voltage ovp pin ovp flag debounce time 10s figure 13. ovp thresholds and timing table 7. programmable options fo r open-loop protection (olp) parameter values or options comments debounce time 10 s (fixed) minimum du ration of pulse to be considered propagation delay 200 ns (fixed) does not include debounce actions for olp immediate shutdown and wait for pson; disable pwm until the flag is cleared; shut down and soft start; ignore (do nothing) register 0xfe02, bits[7:6]
data sheet ADP1047/adp1048 rev. 0 | page 17 of 84 power factor correction control loop the ADP1047 / adp1048 implement the average current mode power factor correction control loop using a traditional multi- plier approach. the implementation of the loop is digital, and all the signals are converted from analog to digital before they are processed by the control loop. - adcs are used to achieve high performance, cost-effective implementation. each adc has its own dedicated voltage reference. digital compensation filters the ADP1047 / adp1048 are digital pfc controllers with ac power monitoring. they are implemented in the digital domain using a dedicated state machine, which allows the user to program the loop response specifically, with no need for external loop compensation. the detailed control loop configuration is illustrated in figure 14 . v ref is the digital reference voltage setting; v fb is the sensed feed- back voltage of the output. the difference between v ref and v fb is processed first by the voltage loop filter (h v ). its output, v ea , is then multiplied by the instantaneous rectified input voltage, v ac , and divided by the square of the rms value of v ac . the result, i ref , is used as the reference signal for the current. the output of the current loop filter (h i ) is the duty cycle command. the mathematical expression is 2 _ rmsac acea ref v vv i = both the voltage loop and current loop digital compensating filters, h v (z) and h i (z), are programmable. the filter transfer function in the digital domain is () 1 256 ? ? ? ? ? ? ? ? = z a z bkh(z) where: a is the filter zero. b is the filter gain. k is related to the switching frequency. the frequency gains and zero locations can all be programmed individually to tailor the loop response to the application. it is recommended that the analog devices, inc., gui software be used to program the filter (see the software gui section). the gui displays the filter response in bode plot format and can be used to calculate all stability criteria for the power supply. optimized compensation filters instead of a single programmable compensation filter, the ADP1047 / adp1048 offer the following filter presets so that the dynamic response of the control loop can be tailored to optimize different operating conditions. ? low line current filter ? high line current filter ? fast voltage compensation filter the ADP1047 / adp1048 can be configured to switch auto- matically between the high and low line filters when the rms value of the ac line crosses the programmed threshold between the high and low lines. (the high line threshold is programmed in register 0xfe35; the low line threshold is programmed in register 0xfe36.) the ADP1047 / adp1048 check for the value of the rms input voltage at each half line cycle. when a transition between the high and low line threshold is detected, the part waits for four full line cycles before switching to the correct filter at the zero crossing of the input line cycle. this is done to avoid spurious transitions due to a missing or distorted voltage line cycle. during soft start, one of four combinations of filters can be used, depending on whether the fast loop mode is enabled and whether the high line or low line is detected for soft start (see table 8 ). 09696-010 + ? v fb h v (z) v ref v ea + ? i l i ref duty cycle h i (z) v ac v 2 ac_rms figure 14. control loop digital filters table 8. summary of the pfc digital compensation filters for soft start line filter normal compensation filter fast voltage compensation filter high line high line current filter, normal voltage fi lter high line current filter, fast voltage filter low line low line current filter, normal voltage fi lter low line current filter, fast voltage filter
ADP1047/adp1048 data sheet rev. 0 | page 18 of 84 fast loop mode during transients, a fast loop mode is enabled to allow for faster loop responses. typical timing can be seen in figure 15 . the fast loop mode has separate sett ings and can be programmed to respond quickly to load transients. the user can disable the fast loop mode if it is not required by the application. programmable range i load v out fast loop v rec program- mable delay (0 to 7 half line cycles) 09696-011 figure 15. fast loop for transient response improvement when fast loop mode is enabled and the feedback output voltage is out of range from the desired reference value (programmable band of 1.5%, 3%, 6%, or 12%, set in register 0xfe24), the ADP1047 / adp1048 enter fast loop mode. to ensure a smooth transition, the ADP1047 / adp1048 switch from the regular filter to the fast loop filter at the zero crossing of the rectified input voltage. when the output voltage returns to regulation within the programmed band, the controller switches back (after a programmable delay of 0 to 7 half line cycles) to the normal loop at the next zero crossing of the rectified input voltage. if the output voltage does not return to regulation within the programmed band after a fixed time of 630 ms, the control loop automatically switches back to the normal loop. in the normal compensation loop, the sampling frequency of the output voltage is the same as the ripple oscillation frequency (which is commonly 100 hz or 120 hz). during fast loop operation, the feedback voltage is sampled at 1.5 khz, and the fast filter is applied to regulate the output voltage. the output voltage is averaged and decimated at 1.5 khz (see figure 16 ). 09696-012 vfb vfb error fast loop vfb fast error normal filter @ 100hz fast filter @ 1.5khz figure 16. fast loop operation based on the requirements of the application, the user can enable or disable the fast loop mode by programming register 0xfe24. it is recommended that fast loop mode be enabled for the ADP1047 / adp1048 during large load transients. the fast loop mode settings are also used during soft start, even when the fast loop is disabled. pulse-width modulation the ADP1047 / adp1048 can implement either leading edge or trailing edge modulation. trailing edge modulation is the more popular modulation scheme. using trailing edge modulation, the rms ripple current in the bulk capacitors can be reduced when used with downstream converter synchronization. it is recommended that the analog devices, inc., gui software be used to program pwm (see the software gui section). duty cycle minimum/maximum limits the ADP1047 / adp1048 allow the user to program the mini- mum off time and the minimum on time for the pwm outputs separately, thereby allowing the minimum and maximum duty cycles to be set. the minimum off time represents the minimum time that the pwm is low during each switching cycle. it can be programmed from 40 ns to 1.2 s in steps of 80 ns using register 0xfe15, bits[3:0]. in this way, the maximum duty cycle can be clamped between 96% and 99.8% at the minimum frequency and between 48.8% and 96.8% at the maximum frequency. the minimum on time is the smallest pwm pulse that the mod- ulator generates on the pwm output. it can be programmed from 0 ns to 1200 ns in steps of 80 ns using register 0xfe15, bits[7:4]. auxiliary pwm output ( ADP1047 only) for the ADP1047 , the pwm2 pin is the output for the auxiliary pwm, which can be independent of the main pwm output. pwm2 can be used as the control signal for auxiliary switching in the zero-voltage transition soft-switched pfc boost circuit.
data sheet ADP1047/adp1048 rev. 0 | page 19 of 84 switching frequency programming the switching frequency of the pwm outputs can be programmed from 30 khz to 400 khz using register 0xfe1b, bits[5:0] (see table 9 ). table 9. switching frequency settings from 30 khz to 400 khz (register 0xfe1b, bits[5:0]) frequency setting (decimal) frequency (khz) frequency setting (decimal) frequency (khz) frequency setting (decimal) frequency (khz) frequency setting (decimal) frequency (khz) 0 30.05 16 107.76 32 204.92 48 277.78 1 32.55 17 111.61 33 208.33 49 284.09 2 35.51 18 115.74 34 211.86 50 290.70 3 39.06 19 120.19 35 215.52 51 297.62 4 43.40 20 125.00 36 219.30 52 304.88 5 48.83 21 130.21 37 223.21 53 312.50 6 52.06 22 135.87 38 227.27 54 320.51 7 55.80 23 142.05 39 231.48 55 328.95 8 60.10 24 148.81 40 235.85 56 337.84 9 65.10 25 156.25 41 240.38 57 347.22 10 71.02 26 164.47 42 245.10 58 357.14 11 78.13 27 173.61 43 250.00 59 367.65 12 86.81 28 183.82 44 255.10 60 378.79 13 97.66 29 195.31 45 260.42 61 390.63 14 100.81 30 198.41 46 265.96 62 403.23 15 104.17 31 201.61 47 271.74 63 403.23
ADP1047/adp1048 data sheet rev. 0 | page 20 of 84 line fault protections and soft start sequencing pson operation to comply with pmbus standards, the pfc circuit controlled by the ADP1047 / adp1048 can be turned on and off by the hardware pson pin and/or the software pson command. the setting of bit 2 in register 0x02 determines whether the pson pin and/or the pson command is used. if the pson pin is used, the pin can be configured to be either active high or active low (see table 18 ). ac line detection the ADP1047 / adp1048 are capable of detecting several parameters of the ac line input voltage and taking the appro- priate programmed actions when necessary. the detection is a combination of time and voltage measurements and is implemented via the vac pin, which detects the rectified ac input voltage. this allows early detection of ac line faults and early warning for the host system, thereby increasing reliability. five main parameters are related to ac line detection. ? vac_line_period (register 0xfe85) ? vac_threshold_set (register 0xfe25) ? vac_threshold_read (register 0xfe26) ? min_ac_period_set (register 0xfe27) ? max_ac_period_set (register 0xfe28) ac line period and zero crossing the input ac line period is measured every half period of the ac line cycle and is reported in the vac_line_period register (register 0xfe85). during the first 40 ms, the ac line period is measured between two consecutive falling crossings of the threshold value, which is set in the vac_threshold_set register (register 0xfe25, bits[6:0]). the ac line period is then measured between two consecutive falling crossings and compared to the average value of the input line voltage, which is calculated during each half line period. the vac average reading can be found in the vac_ threshold_read register (register 0xfe26, bits[6:0]) . if the measured period is larger than max_ac_period_set or smaller than min_ac_period_set, the default, max_ac_ period_set, is used as the value of the period. as shown in figure 17 , the two consecutive crossing points, b and c, are used to determine the zero-crossing point of the ac line. the middle point between b and c is calculated as the zero-crossing point. this information is used by the control loop, as well as the power metering block. vac average (reg 0xfe26) vac threshold (reg 0xfe25) half ac line period ab c 09696-013 figure 17. ac line period detection
data sheet ADP1047/adp1048 rev. 0 | page 21 of 84 ac line value detection to operate, the controller must detect the ac line value. at startup, the controller waits for the pson signal (hardware pson, software pson, or both, depending on how the part is programmed). when the pson signal is present, the controller looks for the ac line period and value (see figure 18 ). v in_on (reg 0x35) vac brown_out flag (reg 0xfe80[2]) 09696-014 figure 18. vac detection for startup the start-up value for the ac line used by the controller to initiate the start-up procedure is stored in the vin_on register (register 0x35). this value is the minimum rms value of the ac line required for the system to start up. the controller measures the value of vac at every half line cycle and compares it with vin_on. if vac is larger than the value in the vin_on register, the soft start procedure is initiated and the brown_out flag is reset. ac line early fault detection after the vin_on limit is crossed and the system starts up, the controller constantly monitors the condition of the ac line (see figure 19 ). timer 1/4 vac vin_low flag (reg 0x7c[3]) vin_off (reg 0x36) 09696-015 timer 1/4 figure 19. ac line early fault detection to provide early detection of ac line faults, the instantaneous value of vac is compared to the vin_off value in register 0x36. if vac remains below the vin_off threshold for a time longer than the programmed period, the vin_low flag is set in register 0x7c. the programmed period can be either a frac- tion of the detected ac line period (one-quarter or one-half) or it can be an absolute time (2 ms or 4 ms); the value is set in register 0xfe2e. the controller does not take any action, but the vin_low signal can be used to set the ac_ok signal and to trigger immediate actions in the power system. the vin_off threshold is intended solely to provide early warning of problems on the ac line; it is not used to shut down the power supply. the vin_uv_fault_limit register (register 0x59) is used for that purpose. vac max = 265v ac adc input range = 1.6v vac min = 90v ac 09696-016 vin_ov_fault_limit = 270v ac (reg 0x55) vin_on = 85v ac (reg 0x35) vin_off = 70v ac (reg 0x36) vin_uv_fault_limit = 70v ac (reg 0x59) vin_uv_warn_limit = 80v ac (reg 0x58) high line limit (vac th ) = 180v (reg 0xfe35) low line limit (vac th ) = 150v (reg 0xfe36) hysteresis zone figure 20. input voltage limits
ADP1047/adp1048 data sheet rev. 0 | page 22 of 84 soft start procedure the pson signal is used to enable or disable the pfc stage. after pson is asserted, the ADP1047/ adp1048 start monitor- ing vac and, if the ac line conditions are met, they initiate the soft start procedure, as shown in figure 21 . startup is gated by the rms value of the ac line voltage measured on one half period of the ac line frequency. when vac is above the vin_on value, the brown_out flag is reset and the soft start sequence is initiated. at the same time, the inrush delay time and soft start delay time timers begin. both of these timers can be programmed to count 0 to 7 line cycles (or 0 to 14 half line cycles in steps of 2). after the inrush delay time programmed in register 0xfe2e, bits[2:0], the inrush flag is reset and the inrush signal (pin 17) is asserted, closing the inrush current relay. (note that the inrush flag is active low.) the inrush signal is set at the zero crossing of the ac voltage, if this crossing is detected. this setting allows zero voltage turn-on if a solid-state switch is used (zero voltage turn-on is not relevant with mechanical relays). after the soft start delay time (programmed in register 0xfe2d, bits[5:3]), the output voltage is ramped up according to the soft start time programmed in register 0xfe2d, bits[2:0]. some of the flags can be blanked during soft start so that the programmed action of the flag does not take place if the flag is set during the soft start period (see register 0xfe08 and register 0xfe09). when output voltage regulation is reached and all flags are ok, the power_good# flag is reset and the pgood signal (pin 16) is set to logic level 1. (note that the power_good# flag is active low.) the soft start time can be programmed to one of eight values: 112 ms, 168 ms, 224 ms, 280 ms, 392 ms, 504 ms, 616 ms, or 728 ms (set in register 0xfe2d, bits[2:0]). the soft start delay time (register 0xfe2d, bits[5:3]) can be programmed from 0 to 7 full line cycles in increments of 1 (that is, two of the rectified half line cycles). the inrush delay time (register 0xfe2e, bits[2:0]) can be pro- grammed from 0 to 7 full line cycles in increments of 1 (that is, two of the rectified half line cycles). if no zero crossings are detected, the programmed maximum ac line period, max_ac_period_set (register 0xfe28), is used. line fault protections line faults occur when the ac line is not behaving correctly and include anomalies such as a missing ac line cycle (can be partial), brownout, or high distortion levels. when a line fault occurs, the ADP1047/ adp1048 can be programmed to react according to the situation. v in_on (reg 0x35) vin_off (reg 0x36) vac vin_low flag (reg 0x7c[3]) brown_out flag (reg 0xfe80[2]) inrush pin vout 09696-017 soft start time (reg 0xfe2d[2:0]) inrush delay time = 2 (reg 0xfe2e[2:0]) soft start delay time = 3 (reg 0xfe2d[5:3]) figure 21. soft start and inrush current control timing
data sheet ADP1047/adp1048 rev. 0 | page 23 of 84 missing ac line cycles figure 22 shows examples of the typical missing ac line cycles fault. the vin_low flag is set when the instantaneous voltage is below vin_off for more than a quarter or half line cycle (depending on how it is programmed). this flag can be used as an early warning to the system via the ac_ok pin when more than a half cycle is missing. the brown_out flag is also set; this flag does not cause a shutdown. if any other flag that is programmed for shut down is set (in this example, vout_uv_fault), the power supply shuts down, the inrush pin is asserted, and the controller prepares for the next soft start cycle. if the brown_out flag is cleared before vout drops below the vout_uv_fault_limit value (register 0x44), opera- tion resumes in normal mode (or fast loop mode if enabled); otherwise, if vout drops below vout_uv_fault_limit, the inrush pin is reset and a new soft start cycle is started. pson delay the pson start delay is programmable using register 0xfe06, bits[3:2]. four options are available: 0 ms, 50 ms, 250 ms, and 1000 ms. brownout conditions brownout is another typical line fault condition in which the line drops below the minimum specified operating level. this level can be set with vin_uv_fault_limit (register 0x59). this flag can be programmed according to the standard pmbus flag response. for example, it can be programmed to shut down and restart after a certain delay. during brownout, there are other conditions that can occur, such as input overcurrent or output undervoltage. each of these faults can be programmed to shut down or disable the output, based on the response action. vin_on (reg 0x35) vin_off (reg 0x36) vac vin_low flag (reg 0x7c[3]) brown_out flag (reg 0xfe80[2]) inrush pin vout 09696-018 vout_uv_fault_limit (reg 0x44) soft start time (reg 0xfe2d[2:0]) inrush delay time (reg 0xfe2e[2:0]) figure 22. line fault (missi ng cycles) timing diagram 09696-019 shutdown v ac vin_on (reg 0x35) vin_uv_fault_limit (reg 0x59) brown_out flag (reg 0xfe80[2]) vin_uv_fault flag (1 cycle debounce) inrush pin figure 23. brownout timing di agram (vin_uv_fault_response register programm ed to shut down after a one-cycle debounce)
ADP1047/adp1048 data sheet rev. 0 | page 24 of 84 advanced input power metering the ADP1047 / adp1048 monitor and communicate critical information, including input and output voltage, input and output current, temperature, and efficiency. they also monitor a n d c o m m u n i c a t e o v p, u v p, o c p, o t p, a n d o p e n - l o o p p r o t e c - tion functions. an i 2 c interface reads all these values and flags and programs their thresholds. the on-chip eeprom can be used to store all of the settings for the thresholds. true rms values are calculated at the end of each half ac line cycle by integrating the instantaneous values across each line cycle. these values have a resolution of 11 bits and are used to calculate the average, but are not available to be read through the pmbus interface. the averaging window is programmable from zero full line cycles to 4096 full line cycles using register 0xfe3a. at the end of each averaging period, the new value for average power is written to the read_pin register (register 0x97) and is available to be read back through the interface until it is overwritten by the next averaged value at the end of the next averaging period. for this reason, the polling frequency used to read average power through the pmbus interface must be equal to or higher than the averaging window to maintain data integrity. the averaging window is programmable over a wide range of times to accommodate different situations. input voltage, input current, output voltage, and input power are reported in linear format in the following registers: ? input voltage: read_vin (register 0x88) ? input current: read_iin (register 0x89) ? output voltage: read_vout (register 0x8b) ? input power: read_pin (register 0x97) 09696-022 cs+ pgnd vac cs? adc avg avg v in p in i in adc avg 0 line cycles to 4096 line cycles 1 2 3 rms rms rms ac sync figure 24. block diagram of power monitoring table 10. data format and range for v in , i in , p in , and v out metering data mantissa (bits) exponent (n) mini mum range minimum lsb maximum range maximum lsb v in 11 ?3 to ?1 256 v 0.125 v 1024 v 0.5 v i in 11 ?10 to ?5 2 a 0.976 ma 64 a 0.03125 a p in 11 ?4 to +3 256 w 125 mw 32.8 kw 16 w v out 11 ?3 to 0 256 v 0.125 v 2048 v 1 v
data sheet ADP1047/adp1048 rev. 0 | page 25 of 84 power supply system and fault monitoring the ADP1047 / adp1048 have extensive system and fault mon- itoring capabilities. the system monitoring functions include voltage, current, power, and temperature readings. the fault conditions include out of limit for current, voltage, power, and temperature. the limits for the fault conditions are programmable. an extensive set of flags is set when certain thresholds or limits are exceeded. these flags are described in table 11 and table 12 . flag conventions a flag indicates a fault condition; therefore, a flag is set (equal to 1, or high) when the fault or bad condition occurs. good flags, such as power_good# and ac_ok, are active low flags. for example, power_good# = 1 indicates a problem. note that the signals relative to a flag are active high. for example, if the power_good# flag is set to 1, the pgood pin is at logic level 0 because the power_good# flag is inverted at the pin to provide active high signals. manufacturer-specific flags the manufacturer-specific flags are flags that are not covered by the pmbus specification. some flags simply indicate a condition (typically, warning flags). the response to some of the flags is individually programmable (typically, fault flags). there is also a set of latched fault registers. these registers con- tain the same flags, but the flags remain set to allow users to detect an intermittent fault. reading a latched register resets the flags in that register. the latched fault registers are register 0xfe80, register 0xfe81, and register 0xfe82. table 11. summary of manufacturer-specific flags bit name address description (1 = flag set) action max_modulation 0xfe80[7] the maximum modulation limit is reached. min_modulation 0xfe80[6] the minimum modulation limit is reached. olp 0xfe80[5] signals a difference of more than ~ 100 mv between the vfb and ovp signals (one of the two voltage dividers is probably disconnected or malfunctioning). programmable fast_ovp 0xfe80[4] the threshold set for the comparat or on the ovp pin has been crossed. programmable ac_period 0xfe80[3] the controller is not able to detect the ac line period; the maximum value of the period is used an d this flag is set. brown_out 0xfe80[2] vac is lower th an the value stored in vin_on (r egister 0x35). can set ac_ok flag soft_start 0xfe80[1] the system is in soft start sequence; fast loop filter is in use. inrush 0xfe80[0] inrush control relay is off. inrush pin (can also set ac_ok flag) eeprom_unlocked 0xfe81[6] eeprom is unlocked and its contents can be written. eeprom_crc 0xfe81[5] the downloaded cont ents of the eeprom are incorrect. i2c_address 0xfe81[4] the resistor on the add pin has a value that can cause an error in the address assignment (the address falls too close to the threshold between two addresses). low_line 0xfe81[3] the input voltage is higher than the high line threshold. programmable fast_ocp 0xfe81[2] the threshold set for the comparat or on the ilim pin has been crossed. programmable sync_lock 0xfe81[1] external synchr onization frequency is locked. ac_ok 0xfe81[0] the output of the ac_ok pin is low. (this flag is a programmable combination of other internal flags and refers to the condition of the input voltage.) ac_ok pin low_power 0xfe82[5] the input power has dropped below the threshold for low power mode operation. programmable fast_loop 0xfe82[4] the fast loop co mpensation filter is in use. can set power_good# flag vcore_ov 0xfe82[3] an overvoltage condition is present on the vcore rail. programmable vdd_3.3v_ov 0xfe82[2] an overvoltage conditio n is present on the vdd rail. programmable vdd_3.3v_uv 0xfe82[1] an undervoltage condit ion is present on the vdd rail. shutdown
ADP1047/adp1048 data sheet rev. 0 | page 26 of 84 standard pmbus flags when the corresponding bit of a standard pmbus flag is set in the status_word or status_byte register, the programmed action takes place as shown in figure 25 . figure 25 shows the bits in the six standard pmbus fault response registers: register 0x41, register 0x45, register 0x50, register 0x56, register 0x5a, and register 0x5c. all six pmbus fault response registers follow the same format. for more infor- mation, see the pmbus fault flag response section. 09696-023 1 0 = s h u t d o w n t h e n r e t r y 0 1 = c o n t i n u e t h e n r e t r y fault cleared 11 = disable output fault not cleared output disabled response (bits[7:6]) retry setting (bits[5:3]) delay time (bits[2:0]) normal operation 00 = do nothing flags are ignored if blanked soft start delay time (bits[2:0]) shut down retry setting (bits[5:3]) 000 = no retries (off) 001 to 110 = try 1 to 6 times 111 = retry forever if flag still active 01 = shut down (after debounce) 10 = immediate shutdown figure 25. standard pmbus fault response table 12. summary of standard pmbus flags implemented on the ADP1047 / adp1048 name address description action status_byte (0x78) pson_off 0x78[6] power supply on signal: this flag indicates that the pson signal (hardware or software) is inactive. vout_ov 0x78[5] general output overvoltage fault. this flag is a combination (or) of any output overvoltage flag: register 0x7a[7] and register 0xfe80[4] (fast_ovp). programmable vin_uv 0x78[3] general input unde rvoltage fault (same data as in register 0x7c[4]). programmable temperature 0x78[2] temperature fault or warning. programmable cml 0x78[1] communications, memory, or logic fault. none_of_the_above 0x78[0] a fault or warning not listed in register 0x78[7:1]. status_word (0x79) vout 0x79[15] any fault or warning on the output volt age (overvoltage, undervoltage, fast ovp, or accurate ovp). input 0x79[13] input voltage, input current, or input power fault or warning (same data as in register 0x7c, bits[7:0]). mfr 0x79[12] manufacturer-specific fault or warning (same data as in register 0xfe80, register 0xfe81, and register 0xfe82). power_good# 0x79[11] power good. this flag is a programmable combination of other internal flags and refers to the condition of the outp ut voltage. this flag sets the pgood pin. the power_good# flag is an in verted version of the pgood pin. pgood pin unknown 0x79[8] a fault or warnin g not listed in bits[15:1].
data sheet ADP1047/adp1048 rev. 0 | page 27 of 84 name address description action status_vout (0x7a) vout_ov_fault 0x7a[7] the output voltage is above the vout_ov_fault_limit. programmable vout_ov_warn 0x7a[6] the output voltage is above the vout_ov_warn_limit. vout_uv_warn 0x7a[5] the output voltag e is below the vout_uv_warn_limit. vout_uv_fault 0x7a[4] the output voltage is below the vout_uv_fault_limit. programmable status_input (0x7c) vin_ov_fault 0x7c[7] the input voltage on vac is larg er than the value in vin_ov_fault_limit. programmable vin_uv_warn 0x7c[5] the input voltage on vac is smaller than the value in vin_uv_warn_limit. vin_uv_fault 0x7c[4] the input voltage on vac is sma ller than the value in vin_uv_fault_limit. programmable vin_low 0x7c[3] vac is lower than vin_off. this signal shuts down the power supply. can set ac_ok flag iin_oc_fault 0x7c[2] the input current measured on the cs adc is larger than the value in iin_oc_fault_limit. programmable iin_oc_warn 0x7c[1] the input current measured on the cs adc is larger than the value in iin_oc_warn_limit. can set ac_ok flag pin_op_warn 0x7c[0] input overpower warning. status_temperature (0x7d) ot_fault 0x7d[7] the measured temperature is ab ove the value set in ot_fault_limit. programmable ot_warn 0x7d[6] the measured temperature is above the value set in ot_warn_limit. pmbus fault flag response all standard pmbus fault response registers follow the same format. the six standard pmbus fault response registers are ? vout_ov_fault_response (register 0x41) ? vout_uv_fault_response (register 0x45) ? ot_fault_response (register 0x50) ? vin_ov_fault_response (register 0x56) ? vin_uv_fault_response (register 0x5a) ? iin_oc_fault_response (register 0x5c) the standard pmbus fault response registers are composed of eight bits: bits[7:6] define the response type, bits[5:3] define the retry settings, and bits[2:0] contain the delay information. bits[7:6] define the response type as follows: ? bits[7:6] = 00 (ignore). when the corresponding fault flag is set, no action is taken and the power supply continues to operate normally. ? bits[7:6] = 01 or 10 (shutdown and retry). when the cor- responding fault flag is set, the system shuts down and then retries for the number of times programmed in bits[5:3]. the difference between the 01 and 10 options is that when bits[7:6] = 01, a debounce (programmed in bits[2:0]) is applied to the flag. ? bits[7:6] = 11 (disable output). when the corresponding fault flag is set, the system does not enter a shutdown/soft start sequence. instead, the output is disabled indefinitely until the flag is cleared. care must be taken when selecting this option because it may cause the system to stall in an endless loop. concurrent faults when multiple faults occur at the same time, the state machine executes the response that has the highest priority. flag priority is determined by the response of the faults as determined by bits[7:6]. the higher the number in these two bits, the higher the priority. for example, if ovp is programmed to disable the output (bits[7:6] = 11) and ocp is programmed to shut down and retry after a delay (bits[7:6] = 01), and both faults occur at the same time, the ovp action is executed first. if the ovp con- dition is cleared and the ocp flag is still set, the programmed action for ocp is executed. if two or more faults occur at the same time and all the faults have the same response priority, the fault with the smallest retry setting takes priority. for example, if one fault has a retry setting programmed to 011 and the other has a retry setting of 001, the lower number of retries is executed.
ADP1047/adp1048 data sheet rev. 0 | page 28 of 84 manufacturer-specific flag response manufacturer-specific flags follow a different response from the standard pmbus flags because these flags are much faster and, in some cases, operate on a pulse-by-pulse basis. fast ocp flag response (register 0xfe00) the fast ocp flag responds to an overcurrent condition that occurs on the comparator connected to the ilim pin. this comparator performs a pulse-by-pulse current limiting func- tion (see the fast overcurrent protection (ilim pin) section). four different actions can be programmed for this flag using bits[7:6]. regardless of the programmed flag response, the pwm pulse is always terminated when the threshold programmed for the comparator is crossed. ? 00 (ignore, do nothing). no action is taken. the pwm pulses are still terminated as long as the ocp condition persists. ? 01 (shut down and soft start). the power supply is shut down, and a soft start sequence is initiated after the delay that is programmed in the iin_oc_fault_response register (register 0x5c, bits[2:0]). ? 10 (shutdown and wait for pson). after the number of switching cycles programmed in bits[5:4], the power supply is shut down until the pson signal is received. ? 11 (disable the pwm until the flag is cleared). after the number of switching cycles programmed in bits[5:4], the pwm is disabled until the flag is cleared; no soft start is initiated. fast ovp flag response (register 0xfe01) the fast ovp flag responds to an overvoltage condition on the programmable comparator connected to the ovp pin. this comparator constantly monitors the output voltage and its operation (see the fast overvoltage protection (ovp pin) section). four different actions can be programmed for this flag. ? 00 (ignore, do nothing). no action is taken. ? 01 (shut down and soft start). the power supply is shut down, and a soft start sequence is initiated after the delay programmed in the vout_ov_fault_response register (register 0x41, bits[2:0]). ? 10 (immediate shutdown and wait for pson). the power supply is shut down until the pson signal is received. ? 11 (disable the pwm until the flag is cleared). the pwm is disabled until the flag is cleared; no soft start is done. olp flag response (register 0xfe02) the olp flag responds to differences between the ovp and vfb pins. open-loop protection detects a difference in voltage in excess of ~100 mv, which equates to approximately 6.6% of the full-scale range (see the open-loop protection section). four different actions can be programmed for this flag. ? 00 (ignore, do nothing). no action is taken. ? 01 (shut down and soft start). the power supply is shut down, and a soft start sequence is initiated after the delay programmed in the vout_ov_fault_response register (register 0x41, bits[2:0]). ? 10 (immediate shutdown and wait for pson). the power supply is shut down until the pson signal is received. ? 11 (disable the pwm until the flag is cleared). the pwm is disabled until the flag is cleared; no soft start is done. vdd and vcore ov flag response (register 0xfe03 and register 0xfe04) these two flags respond to an overvoltage condition on the vdd (3.3 v) and vcore (2.5 v) rails. these rails must be properly decoupled and filtered to guarantee proper operation of the digital controller. the controller can be programmed to ignore the flags or to shut down and restart. a debounce time of 2.56 s or 660 s can be set. the controller can also be instructed to reload the contents of the eeprom upon restart or to resume operation without reloading the eeprom contents. reloading the contents of the eeprom to ram prevents device malfunction if the ram contents have been corrupted during the overvoltage condition. 09696-024 blanking and debounce terminate pwm pulse fast ocp ilim flag set, programmed actions timeout 1 to 8 times figure 26. fast ocp flag
data sheet ADP1047/adp1048 rev. 0 | page 29 of 84 monitoring functions voltage, current, power, and temperature measurements are taken by the ADP1047 / adp1048 . these values are stored in the following registers and can be read through the pmbus interface. ? input voltage measurement (register 0x88) ? output voltage measurement (register 0x8b) ? input current measurement (register 0x89) ? input power measurement (register 0x97) ? temperature measurement (register 0xfe86) first error fault the ADP1047 / adp1048 provide a flag_fault_id register (register 0xfe07) that records the first fault that causes a system shutdown. for example, if the overtemperature (ot) fault causes the system to shut down, the ot_fault flag (0011) is stored in the flag_ fault_id register (register 0xfe07, bits[3:0]). in addition, the flag id of the fault that occurred before the fault that caused the system shutdown is included in bits[7:4] of register 0xfe07. the contents of this register are stored until read by the user. the flag id is also saved in eeprom when the shutdown occurs. in this way, it is possible to determine the cause of a shutdown in case of system failure. overtemperature protection (otp) if the temperature sensed at the rtd pin exceeds the program- mable fault threshold, the otp flag is set, and the power supply can be programmed to shut down. a ptc or ntc thermistor can be used. to set the fault and warning thresholds for otp, program register 0xfe19 and register 0xfe1a, respectively. to set the temperature hysteresis for the fault and warning thresholds, program register 0xfe3f. the response to an otp fault flag is programmable in register 0x50. ac_ok and pgood signals the ADP1047 / adp1048 have two digital status pins: ac_ok and pgood. both signals represent an or function for a pro- grammable list of internal flags. users can blank some of these flags to tailor the ac_ok and pgood signals to their needs using register 0xfe0b and register 0xfe0a, respectively. when the signals on the ac_ok and pgood pins are set, the corresponding internal flag is also set. the programmable delay block acts like a debounce. that is, the signal must be active for at least the duration of the programmed delay before the flag is set. the debounce times for the ac_ok and pgood pins can be programmed separately in register 0xfe05. 09696-025 reg 0xfe0a programmable delay block pgood_flags_list (programmable list of flags) pgood reg 0xfe0b programmable delay block ac_ok_flags_list (programmable list of flags) ac_ok figure 27. ac_ok and pgood signals table 13. flags available to program the ac_ok and pgood pins ac_ok_flags_list (register 0xfe0b) 1 pgood_flags_list (register 0xfe0a) 1 vin_low (always checked) vout_ov_fault (always checked) vin_uv_fault (bit 7) vout_uv_fault (bit 7) vin_uv_warn (bit 6) vout_ov_warn (bit 6) iin_oc_fault (bit 5) fast_ovp (bit 5) iin_oc_warn (bit 4) olp (bit 4) fast_ocp (bit 3) fast_ocp (bit 3) ac_line_period (bit 2) iin_oc_fault (bit 2) brown_out (bit 1) ot_fault (bit 1) inrush (bit 0) fast_loop (bit 0) 1 to blank one or more flags so that the ac_ok or pgood pin ignores it, set the corresponding bit to 1 in register 0xfe0a or reg ister 0xfe0b.
ADP1047/adp1048 data sheet rev. 0 | page 30 of 84 advanced features the advanced features of the ADP1047 / adp1048 include ? frequency dithering for emi noise minimization ? pwm frequency synchronization with external source ? smart output voltage: real-time efficiency optimization by changing the output voltage based on ac line and output power ? smart switching frequency: real-time efficiency optimization by changing the switching frequency ? current loop filter for light load: real-time thd optimization at light load conditions ? phase shedding ( adp1048 only): real-time efficiency optimization by shutting down one phase ? current loop feedforward: power factor and thd optimization at light load conditions ? bridgeless boost operation ( adp1048 only) all advanced features other than bridgeless boost operation are enabled by setting the appropriate bit in register 0xfe4f. frequency dithering (spread spectrum) the pwm signal can be altered digitally to optimize for emi reduction (see figure 28 ). for a wider but lower emi spectrum, the switching frequency varies with the rectified line voltage. the switching cycle changes linearly with time from 87.5% to 112.5% of the nominal value, resulting in a frequency variation of 114% to 89% of the nominal value. to enable frequency dithering, set register 0xfe4f, bit 0, to 1. to configure the dithering period, program register 0xfe1d. 09696-026 time time 1/f dither 2/f dither time switching cycle switching frequency v rec 112.5% t sw t sw 87.5% t sw 114% f sw f sw 89% f sw figure 28. switching frequency dithering control pwm frequency synchronization the part can synchronize the internal pwm clock with an external clock frequency; the external source must be within the minimum and maximum synchronization range programmed in the part. to enable pwm frequency synchronization, set register 0xfe4f, bit 1, to 1. the capture range for the sync period is 87.5% to 112.5% of the programmed switching period. the switching frequency synchronized to the sync pin is limited by the frequency set in register 0xfe1b. the maximum range for the synchronized frequency is from 89% to 114% of the programmed switching frequency. the delay between the external sync signal and the start of the internal switching cycle can be programmed using register 0xfe4c. the part synchronizes to the external clock frequency as follows: 1. the part attempts to determine the external clock period, averaging it over seven cycles (frequency capture mode). 2. after the period of the sync signal is determined, the internal pwm clock is adjusted until the phase is also aligned. at that point, internal and external clocks are synchronized (phase capture mode). 3. each internal switching cycle is terminated after the sync rising edge is detected (pulse-by-pulse synchronization). if the external sync signal is lost at any time or if the period exceeds the minimum/maximum limit, the internal clock goes back to the maximum period set in register 0xfe1b. during the soft start phase, the sync pin is ignored and the clock frequency is not synchronized. interleaved operation of a multiphase pfc circuit is realized by using the sync pin of several ADP1047 / adp1048 controllers. the frequency synchronization feature is optional. when enabled, the switching frequency can be programmed to 1, 1/2, 1/3, or 1/4 of the sync frequency using register 0xfe1e. smart output voltage (load line) to achieve higher efficiency, the output voltage can be programmed according to the load power and input voltage condition (see figure 29 ). to enable the smart output voltage feature, set register 0xfe4f, bit 2, to 1. 09696-027 super high line power voh voh2 voh1 vol2 vol1 p1 p2 100% output voltage high line low line figure 29. smart output voltage control (load line)
data sheet ADP1047/adp1048 rev. 0 | page 31 of 84 three load lines address super high line, high line, and low line input voltage conditions. when the rms value of the input voltage is higher than the super high line input (for example, 250 v), the load line is flat, that is, the output voltage remains at voh, which is independent of the power. to avoid output voltage oscillation when the input voltage is around the super high line level, voltage hysteresis can be programmed using register 0xfe4d. it is recommended that at least 16 v of hysteresis be programmed. when the rms value of the input voltage is lower than the super high line input but higher than the high line threshold, there is a load line between p1 and p2 in terms of power. the output voltage varies between voh1 and voh2 as a linear function of the output power when the output power falls within the range between p1 and p2. the power levels of p1 and p2 are programmable using register 0xfe44 and register 0xfe45, respectively. when the power is below p1, the output voltage remains unchanged at voh1. when the power is higher than p2, the output voltage remains unchanged at voh2. the bottom load line in figure 29 applies when the rms value of the input voltage is lower than the low line threshold. the output voltage varies between vol1 and vol2 as a linear function of the output power when the output power falls within the range between p1 and p2. when the power is below p1, the output voltage remains unchanged at vol1. when the power is higher than p2, the output voltage remains unchanged at vol2. the user can program values for voh, voh2, voh1, vol2, and vol1 using register 0xfe4a, register 0xfe49, register 0xfe48, register 0xfe47, and register 0xfe46, respectively. smart switching frequency for higher efficiency, the switching frequency of the ADP1047 / adp1048 can be programmed according to the load power con- dition (see figure 30 ). to enable the smart switching frequency feature, set register 0xfe4f, bit 3, to 1. 09696-028 power f s f sl full power p th switchin g frequency figure 30. smart switching frequency control the smart switching frequency feature uses two different switching frequencies for heavy load and light load conditions. when the output power is lower than the low power threshold, p th , the pfc circuit switches at the f sl frequency. when the out- put power is higher than p th plus power hysteresis, the circuit switches at the normal set frequency, f s . hysteresis can be programmed in register 0xfe4e. the user can program the values for f sl and p th in register 0xfe1c and register 0xfe32, respectively. current loop filter for light load to achieve low thd under light load conditions, the ADP1047 / adp1048 offer current loop filter presets for light load opera- tion under both high line input and low line input (see figure 31 ). to enable the current loop filter for light load feature, set register 0xfe4f, bit 5, to 1. 09696-029 high line light load high line low line light load light load input power power threshold low line high/low line threshold a c line figure 31. current loop filter at light load condition when the input power drops below the low power threshold, p th (set in register 0xfe32), the current loop filter switches to the light load filter after four full line cycles. when the input power goes above p th plus the programmed hysteresis, the current loop filter switches back to the normal mode filter immediately. this applies to both high line and low line input. phase shedding ( adp1048 only) to achieve high efficiency at light load, the adp1048 can shut down one pwm output under light load conditions. when the input power drops below the low power threshold, p th (set in register 0xfe32), one pwm output is disabled. when the input power goes above the low power threshold plus power hysteresis (set in register 0xfe4e), the pwm resumes operation. to enable phase shedding for the adp1048 , set register 0xfe4f, bit 4, to 1. current loop feedforward current loop feedforward is implemented in the ADP1047 / adp1048 to improve the power factor and reduce thd under light load conditions (see figure 32 ). to enable current loop feedforward, set register 0xfe4f, bit 6, to 1. 09696-030 + + v ac ?v ref + ? i l i ref h i (z) duty cycle figure 32. current loop feedforward
ADP1047/adp1048 data sheet rev. 0 | page 32 of 84 bridgeless boost operation ( adp1048 only) during the positive ac line phase, only one boost stage is effec- tively working. the second one is passive, and the current flows in q2 from the source to the drain. turning the q2 fet fully on during this phase allows conduction losses in q2 to be minimized. the bridgeless boost configuration allows removal of the con- duction losses caused by the input bridge of the pfc converter. in this configuration, it is necessary to drive the two power mosfets separately to achieve the highest efficiency. the adp1048 can provide such signals. the ibal pin is used to detect the ac line phase and zero crossings. note that the maxi- mum rating on the ibal pin is vdd + 0.3 v; therefore, a clamp circuit must be connected to the ibal pin. when the ac line phase becomes negative, the roles of q1 and q2 are reversed, and q2 actively switches while q1 is always on. the phase information is detected from the ac line via the ibal pin. during the soft start phase, both fets are switching as a precau- tionary measure; the same happens when the phase information on the ibal pin becomes corrupted or inaccurate. 09696-031 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 res rtd add sync inrush scl sda vac vfb ovp ibal ilim pgnd agnd cs? 9 10 11 12 16 15 14 13 pson dgnd cs+ pwm2 vcore pwm ac_ok pgood vdd adp1048 v rec relay t3 v out t2 bulk capacito r t1 q2 q1 t1 + t2 + t3 3.3v pmbus ac input figure 33. schematic of bridgeless pfc circuit with the adp1048 09696-032 vac ibal pin pwm pwm2 figure 34. bridgeless boost operation
data sheet ADP1047/adp1048 rev. 0 | page 33 of 84 power supply system calibration and trim the ADP1047 / adp1048 allow the entire power supply to be calibrated and trimmed digitally in the production environ- ment. the device can calibrate items including the output voltage, input voltage, input current, and input power, and it can trim for tolerance errors introduced by sense resistors, current transformers, and resistor dividers, as well as for its own internal circuitry. the part comes factory trimmed at 90% of the input range at a 3.3 v supply, but it can be re-trimmed by the user to compen- sate for the errors introduced by external components. with the exception of the gain and offset trim registers for input power, the trim registers must be unlocked for write access. to unlock the trim registers, write to the trim_password register (register 0xd6). output voltage (vfb) calibration and trim the voltage sense inputs are optimized for sensing signals at 90% of the input range and cannot sense signals greater than 1.6 v. in a high voltage system, a resistor divider is required to reduce the high voltage signal to below 1.6 v. it is recommended that the high voltage signal be reduced to 1 v for best perfor- mance. the resistor divider can introduce errors, which must be trimmed out as follows: 1. turn on the power supply with no load attached. the output voltage is divided down by the feedback resistor divider to supply 1 v across the vfb and agnd pins. 2. use a calibrated multimeter to perform the output voltage reading. 3. adjust the vfb adc gain trim register (register 0xfe41) until the power supply outputs the exact value in the read_vout register (register 0x8b). input voltage (vac) gain and offset trim the input voltage sense point on the power rail requires an external resistor divider to bring the signal within the operating input range of the vac adc (0 v to 1.6 v). the resistor divider can introduce errors, which must be trimmed out as follows: 1. apply the maximum line voltage value to the input of the power supply. the vac resistor divider divides this voltage down at the vac pin. the vac resistor divider is programmed in linear format using the vin scale monitor register (register 0xfe3b). 2. adjust the vac adc gain trim register (register 0xfe40) until the vac value (register 0x88, read_vin) equals the input voltage reading from a calibrated multimeter. this step trims for errors in the resistor divider network. for vac offset trim, adjust the value in register 0xfe53. current sense gain and offset trim the current sense can be calibrated digitally to remove any errors due to external components. 1. apply the maximum load to the output with the low line input voltage. 2. to match the input current reading at the maximum nominal input current, adjust the cs adc gain trim register until the cs value (register 0x89, read_iin) equals the measured result of the input current from calibrated equipment. if the 500 mv input range is used, adjust register 0xfe42. if the 750 mv range is used, adjust register 0xfe7e. for cs offset trim, adjust the va lues in register 0xfe54 (500 mv input range) or register 0xfe7f (750 mv input range). input power gain and offset trim the input power trim has separate trim registers for high line and low line input. 1. apply the maximum load to the output with the low line input voltage. 2. adjust the power metering gain trim for low line input register (register 0xfe34) until the input power value in the read_pin register (register 0x97) equals the measured result of the input power from calibrated equipment. 3. apply the maximum load to the output with the high line input voltage. 4. adjust the power metering gain trim for high line input register (register 0xfe8f) until the input power value in the read_pin register (register 0x97) equals the measured result of the input power from the calibrated equipment. for input power offset trim, adjust the values in register 0xfe33 (for low line input) and register 0xfe8e (for high line input).
ADP1047/adp1048 data sheet rev. 0 | page 34 of 84 pmbus digital communication the pmbus slave allows a device to interface to a pmbus- compliant master device as specified by the pmbus power system management protocol specification (revision 1.1, february 5, 2007). the pmbus slave is a 2-wire interface that can be used to communicate with other pmbus-compliant devices and is compatible in a multimaster, multislave bus configuration. features the function of the pmbus slave is to decode the command sent from the master device and respond as requested. communi- cation is established using an i 2 c-like 2-wire interface with a clock line (scl) and data line (sda). the pmbus slave is designed to externally move chunks of 8-bit data (bytes) while maintaining compliance with the pmbus protocol. the pmbus protocol is based on the smbus specification (version 2.0, august 2000). the smbus specification is, in turn, based on the philips i 2 c bus specification (version 2.1, january 2000). the pmbus incorporates the following features: ? s lave operation on multiple device systems ? 7 -bit addressing ? 1 00 khz and 400 khz data rates ? g eneral call address support ? support for clock low extension ? separate multiple byte receive and transmit fifo ? extensive fault monitoring overview the pmbus slave module is a 2-wire interface that can be used to communicate with other pmbus-compliant devices. its trans- fer protocol is based on the philips i 2 c transfer mechanism. the ADP1047 / adp1048 are always configured as slave devices in the overall system. the ADP1047 / adp1048 communicate with the master device using one data pi n (sda) and one clock pin (scl). because the ADP1047/ adp1048 are slave devices, they cannot generate the clock signal. however, they are capable of clock- stretching the scl line to put the master device in a wait state when they are not ready to respond to the masters request. communication is initiated when the master device sends a command to the pmbus slave device. commands can be read or write commands, in which case, data is transferred between the devices in a byte wide format. commands can also be send commands, in which case, the command is executed by the slave device upon receiving the stop bit. the stop bit is the last bit in a complete data transfer, as defined in the pmbus/i 2 c communication protocol. during communication, the master and slave devices send acknowledge (a) or no acknowledge ( a ) bits as a method of handshaking between devices. see the pmbus specification for a more detailed description of the communication protocol. when communicating with the master device, it is possible for illegal or corrupted data to be received by the pmbus slave device. in this case, the pmbus slave device should respond to the invalid command or data, as defined by the pmbus specifi- cation, and indicate to the master device that an error or fault condition has occurred. this method of handshaking can be used as a first level of defense against programming of the slave device that can potentially damage the chip or system. the pmbus specification defines a set of generic pmbus commands that is recommended for a power management system. however, each pmbus device manufacturer can choose to implement and support certain commands as it deems fit for its system. in addition, the pmbus device manufacturer can choose to implement manufacturer-specific commands whose functions are not included in the generic pmbus command set. the list of standard pmbus an d manufacturer-specific commands can be found in the standard pmbus commands supported by the ADP1047 / adp1048 section and the manufacturer-specific pmbus command section. pmbus address control of the ADP1047 / adp1048 is implemented via the i 2 c interface. the ADP1047 / adp1048 are connected to the bus as slave devices under the control of a master device. the pmbus address of the ADP1047 / adp1048 is set by connecting an external resistor from the add pin to ground. table 14 lists the recommended resistor values and associated pmbus addresses. eight different addresses can be used. table 14. pmbus address settings address add pin resistor value (k) 0x58 10 (or connect directly to agnd) 0x59 30 0x5a 50 0x5b 69 0x5c 89 0x5d 109 0x5e 128 0x5f 148 (or connect directly to vdd) if an incorrect resistor value is used and the resulting i 2 c address is close to a threshold between two addresses, the i2c_address flag is set (bit 4 of register 0xfe81). the recommended resistor values in tabl e 14 can vary by 2 k. therefore, it is recom- mended that 1% tolerance resistors be used on the add pin. the part responds to the standard pmbus broadcast address (general call) of 0x00.
data sheet ADP1047/adp1048 rev. 0 | page 35 of 84 data transfer format overview the pmbus slave follows the transfer protocol of the smbus specification, which is based on the fundamental transfer protocol format of the philips i 2 c bus specification , dated january 2000. data transfers are byte wide, lower byte first. each byte is transmitted serially, most significant bit (msb) first. a typical transfer is diagrammed in figure 35 . see the smbus and i 2 c specifications for an in-depth discussion of the transfer protocols. master to slave slave to master 09696-135 s a aw 7-bit slave address 8-bit data p figure 35. basic data transfer figure 35 through figure 42 use the following abbreviations: s = start condition sr = repeated start condition p = stop condition r = read bit w = write bit a = acknowledge bit (0) a = acknowledge bit (1) a represents the ack (acknowledge) bit. the ack bit is typi- cally active low (logic 0) if the transmitted byte is successfully received by a device. however, when the receiving device is the bus master, the acknowledge bit for the last byte read is a logic 1, indicated by a . command overview data transfer using the pmbus slave is established using pmbus commands. the pmbus specification requires that all pmbus commands start with a slave address with the r/ w bit cleared (set to 0), followed by the command code. all pmbus commands supported by the / follow one of the protocol types shown in through . ADP1047 adp1048 figure 36 figure 42 the pmbus slave module also supports manufacturer-specific extended commands. these commands follow the same protocol as the standard pmbus commands. however, the command code consists of the following two bytes: ? the command code extension, 0xfe ? the extended command code, 0x00 to 0xff using the manufacturer-specific extended commands, the pmbus device manufacturer can add an additional 256 manufacturer-specific commands to its pmbus command set. sp a aw slave address command code 09696-136 master to slave slave to master figure 36. send byte protocol a sp a ad a t a b y t e w slave address command code 09696-137 master to slave slave to master figure 37. write byte protocol a a command code a s p data byte low w slave address a data byte high 09696-138 master to slave slave to master figure 38. write word protocol a sa aw slave address command code p rdata byte sr a slave address 0 9696-139 master to slave slave to master figure 39. read byte protocol aa sa aw slave address command code p r sr slave address 09696-140 master to slave slave to master data byte low data byte high a figure 40. read word protocol a a sa aw slave address command code p a byte count = n data byte 1 data byte n 09696-141 master to slave slave to master figure 41. block write protocol
ADP1047/adp1048 data sheet rev. 0 | page 36 of 84 sr a slave address ar a sa w slave address command code a byte count = n data byte 1 master to slave slave to master p 09696-142 a data byte n figure 42. block read protocol clock generation and stretching the ADP1047 / adp1048 are always pmbus slave devices in the overall system; therefore, the device never needs to generate the clock, which is done by the master device in the system. how- ever, the pmbus slave device is capable of clock stretching to put the master in a wait state. by stretching the scl signal during the low period, the slave device communicates to the master device that it is not ready and that the master device must wait. conditions where the pmbus slave device stretches the scl line low include the following: ? the master device is transmitting at a higher baud rate than the slave device. ? the receive buffer of the slave device is full and must be read before continuing. this prevents a data overflow condition. ? the slave device is not ready to send data that the master has requested. note that the slave device can stretch the scl line only during the low period. also, whereas the i 2 c specification allows indefinite stretching of the scl line, the pmbus specification limits the maximum time that the scl line can be stretched, or held low, to 25 ms, after which the device must release the communication lines and reset its state machine. general call support the pmbus slave is capable of decoding and acknowledging a general call address. the pmbus device responds to both its own address and the general call address (0x00). the general call address enables all devices on the pmbus to be written to simultaneously. note that all pmbus commands must start with the slave address with the r/ w bit cleared (set to 0), followed by the command code. this is also true when using the general call address to communicate with the pmbus slave device. fast mode fast mode (400 khz) uses essentially the same mechanics as the standard mode of operation; the electrical specifications and timing are most affected. the pmbus slave is capable of communicating with a master device operating in standard mode (100 khz) or fast mode. fault conditions the pmbus protocol provides a comprehensive set of fault conditions that must be monitored and reported. these fault conditions can be grouped into two major categories: commu- nication faults and monitoring faults. communication faults are error conditions associated with the data transfer mechanism of the pmbus protocol. monitoring faults are error conditions associated with the operation of the pmbus device, such as output overvoltage protection, and are specific to each pmbus device. these fault conditions are described in the power supply system and fault monitoring section. timeout condition a timeout condition occurs if any single scl clock pulse is held low for longer than the t timeout of 25 ms (min). upon detecting the timeout condition, the pmbus slave device has 10 ms to abort the transfer, release the bus lines, and be ready to accept a new start condition. the device initiating the timeout is required to hold the scl clock line low for at least t timeout max = 35 ms, guaranteeing that the slave device is given enough time to reset its communication protocol.
data sheet ADP1047/adp1048 rev. 0 | page 37 of 84 data transmission faults data transmission faults occur when two communicating devices violate the pmbus communication protocol, as specified in the pmbus specification. see the pmbus specification for more information about each fault condition. corrupted data, pec (item 10.8.1) parity error checking. not supported. sending too few bits (item 10.8.2) transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been sent. not supported; any transmitted data is ignored. reading too few bits (item 10.8.3) transmission is interrupted by a start or stop condition before a complete byte (eight bits) has been read. not supported; any received data is ignored. host sends or reads too few bytes (item 10.8.4) if a host ends a packet with a stop condition before the required bytes are sent/received, it is assumed that the host intended to stop the transfer. therefore, the pmbus does not consider this to be an error and takes no action, except to flush any remain- ing bytes in the transmit fifo. host sends too many bytes (item 10.8.5) if a host sends more bytes than are expected for the corres- ponding command, the pmbus slave considers this a data transmission fault and responds as follows: ? nacks all unexpected bytes as they are received ? flushes and ignores the received command and data ? sets the cml bit in the status_byte register host reads too many bytes (item 10.8.6) if a host reads more bytes than are expected for the corres- ponding command, the pmbus slave considers this a data transmission fault and responds as follows: ? sends all 1s (0xff) as long as the host continues to request data ? sets the cml bit in the status_byte register device busy (item 10.8.7) the pmbus slave device is too busy to respond to a request from the master device. not supported. data content faults data content faults occur when data transmission is successful, but the pmbus slave device cannot process the data that is received from the master device. improperly set read bit in th e address byte (item 10.9.1) all pmbus commands start with a slave address with the r/ w bit cleared (set to 0), followed by the command code. if a host starts a pmbus transaction with r/ w set in the address phase (equivalent to an i 2 c read), the pmbus slave considers this a data content fault and responds as follows: ? acks the address byte ? nacks the command and data bytes ? sends all 1s (0xff) as long as the host continues to request data ? sets the cml bit in the status_byte register invalid or unsupported command code (item 10.9.2) if an invalid or unsupported command code is sent to the pmbus slave, the code is considered to be a data content fault, and the pmbus slave responds as follows: ? nacks the illegal/unsupported command byte and data bytes ? flushes and ignores the received command and data ? sets the cml bit in the status_byte register reserved bits (item 10.9.5) accesses to reserved bits are not a fault. writes to reserved bits are ignored, and reads from reserved bits return 0. write to read-only commands if a host performs a write to a read-only command, the pmbus slave considers this a data content fault and responds as follows: ? nacks all unexpected data bytes as they are received ? flushes and ignores the received command and data ? sets the cml bit in the status_byte register note that this is the same error described in the host sends too many bytes (item 10.8.5) section. read from write-only commands if a host performs a read from a write-only command, the pmbus slave considers this a data content fault and responds as follows: ? sends all 1s (0xff) as long as the host continues to request data ? sets the cml bit in the status_byte register note that this is the same error described in the host reads too many bytes (item 10.8.6) section.
ADP1047/adp1048 data sheet rev. 0 | page 38 of 84 eeprom the ADP1047 / adp1048 have a built-in eeprom controller that is used to communicate with the embedded 8k 8-byte eeprom. the eeprom, also called flash?/ee, is partitioned into two major blocks: the info block and the main block. the info block contains 128 8-bit bytes, and the main block contains 8k 8-bit bytes. the main block is further partitioned into 16 pages, each page containing 512 bytes. overview the eeprom controller provides an interface between the ADP1047 / adp1048 core logic and the built-in flash/ee. the user can control data access to and from the eeprom through this controller interface. separate pmbus commands are avail- able for the read, write, and erase operations to the eeprom. communication is initiated by the master device sending a command to the pmbus slave device to access data from or send data to the eeprom. read, write, and erase commands are supported. data is transferred between devices in a byte wide format. using a read command, data is received from the eeprom and transmitted to the master device. using a write command, data is received from the master device and stored in the eeprom through the eeprom controller. page erase operation the main block consists of 16 equivalent pages of 512 bytes each, numbered page 0 to page 15. page 0 and page 1 of the main block are reserved for storing the default settings and user settings, respectively. the user cannot perform a page erase operation to page 0 or page 1. main block page erase (page 2 to page 15) to erase any page from page 2 to page 15 of the main block, the eeprom must first be unlocked for access. for instructions on how to unlock the eeprom, see the unlock eeprom section. page 2 to page 15 of the main block can be individually erased using the eeprom_page_erase command (register 0xd4). for example, to perform a page erase of page 10, execute the following command: a sp a ad a t a b y t e w slave address command code 09696-137 master to slave slave to master figure 43. example erase command in this example, command code = 0xd4 and data byte = 0x0a. note that it is important to wait at least 35 ms for the page erase operation to complete before executing the next pmbus command. the eeprom allows erasing of whole pages only; therefore, to change the data of any single byte in a page, the entire page must first be erased (set high) for that byte to be writable. subsequent writes to any bytes in that page are allowed as long as that byte has not been written to a low previously. read operation (byte read and block read) read from page 0 and page 1 page 0 and page 1 of the main block are reserved for storing the default settings and user settings, respectively, and are meant to prevent third-party access to this data. to read from page 0 or page 1, the user must first unlock the eeprom (see the unlock eeprom section). after they are unlocked, page 0 and page 1 are readable using the eeprom_data_xx commands, as described in the read from page 2 to page 15 section. note that when the eeprom is locked, a read from page 0 and page 1 returns invalid data. read from page 2 to page 15 data in page 2 to page 15 is always readable, even with the eeprom locked. the data in the eeprom main block can be read one byte at a time or in multiple bytes in series using the eeprom_data_xx commands (command code 0xb0 to command code 0xbf). before executing this command, the user must program the number of bytes to read using the eeprom_num_rd_bytes command (register 0xd2). also, the user can program the offset from the page boundary where the first read byte is returned using the eeprom_addr_offset command (register 0xd3). in the following example, three bytes from page 4 are read from eeprom, starting from the fifth byte of that page. 1. set number of return bytes = 3. a sp a a 0x03 0xd2 w slave address 09696-143 master to slave slave to master 2. set address offset = 5. a s p aa a 0x00 0x05 0xd3 w slave address 09696-144 master to slave slave to master 3. read three bytes from page 4. r s a a as r 0xb4 w slave address slave address p a ... byte count = 0x03 data byte 1 aa data byte 3 09696-145 master to slave slave to master note that the block read command can read a maximum of 256 bytes for any single transaction.
data sheet ADP1047/adp1048 rev. 0 | page 39 of 84 write operation (byte write and block write) before performing a write to page 2 through page 15 of the main block, the user must first unlock the eeprom (see the unlock eeprom section). write to page 0 and page 1 page 0 and page 1 of the main block are reserved for storing the default settings and user settings, respectively. the user cannot perform a direct write operation to page 0 or page 1 using the eeprom_data_xx commands. if the user writes to page 0, page 1 returns a no acknowledge. to program the register con- tents of page 1 of the main block, it is recommended that the store_user_all command be used (command code 0x15). see the save register settings to the user scratch pad section. write to page 2 through page 15 the data in the eeprom main block can be programmed (written to) one byte at a time or in multiple bytes in series using the eeprom_data_xx commands (command code 0xb0 to command code 0xbf). before executing this command, the user can program the offset from the page boundary where the first byte is written using the eeprom_addr_offset command (register 0xd3). if the targeted page has not yet been erased, the user can erase the page as described in the main block page erase (page 2 to page 15) section. in the following example, four bytes are written to page 9, starting from the 256 th byte of that page. 1. set address offset = 256. a s p aa a 0x01 0x00 0xd3 w slave address 09696-146 master to slave slave to master 2. write four bytes to page 9. a sa a byte count = 4 0xb9 w slave address 09696-147 master to slave slave to master p a a ... data byte 1 data byte 4 note that the block write command can write a maximum of 256 bytes for any single transaction. eeprom password on power-up, the eeprom is locked and protected from accidental writes or erases. only reads from page 2 to page 15 are allowed when the eeprom is locked. before any data can be written (programmed) to the eeprom, the eeprom must be unlocked for write access. after it is unlocked, the eeprom is opened for reading, writing, and erasing. on power-up, page 0 and page 1 are also protected from read access, and the eeprom must first be unlocked to read these pages. unlock eeprom to unlock the eeprom, perform two consecutive writes with the correct password (default = 0xff) using the eeprom_ password command (register 0xd5). the eeprom_ unlocked flag (bit 6 of register 0xfe81) is set to indicate that the eeprom is unlocked for write access. lock eeprom to lock the eeprom, write any byte other than the correct password using the eeprom_password command (register 0xd5). the eeprom unlock flag is cleared to indicate that the eeprom is locked from write access. change eeprom password to change the eeprom password, the eeprom must first be unlocked. to change the eeprom password, first write the correct password using the eeprom_password command (register 0xd5). immediately write the new password using the eeprom_password command. the password is now changed to the new password. downloading eeprom settings to internal registers download user settings to registers the user settings are stored in page 1 of the eeprom main block. these settings are downloaded from the eeprom into the registers under the following conditions: ? o n power-up. the user settings are automatically down- loaded into the internal registers, powering the part up in a state previously saved by the user. ? o n execution of the restore_user_all command (command code 0x16). this command allows the user to force a download of the user settings from the eeprom main block, page 1, into the internal registers. download factory settings to registers the factory default settings are stored in page 0 of the eeprom main block. the factory settings can be downloaded from the eeprom into the internal registers using the restore_ default_all command (command code 0x12). when this command is executed, the eeprom password is also reset to the factory default setting of 0xff.
ADP1047/adp1048 data sheet rev. 0 | page 40 of 84 saving register settings into eeprom the register settings cannot be saved to the factory scratch pad located in page 0 of the eeprom main block. this is to prevent the user from accidentally overriding the factory trim settings and default register settings. save register settings to the user scratch pad the register settings can be saved to the user scratch pad located in page 1 of the eeprom main block using the store_user_all command (command code 0x15). before this command can be executed, the eeprom must first be unlocked for writing (see the unlock eeprom section). after the register settings are saved to the user scratch pad, any subsequent power cycle automatically downloads the latest stored user information from the eeprom into the internal registers. note that execution of the store_user_all command automatically performs a page erase to page 1 of the eeprom main block, after which the registers are stored in eeprom. therefore, it is important to wait at least 35 ms for the operation to complete before executing the next pmbus command. eeprom crc checksum as a simple method of checking that the values downloaded from eeprom and the internal registers are consistent, a crc checksum is implemented. ? w hen the data from the internal registers is saved to the eeprom (page 1 of the main block), the total number of 1s from all the registers is counted and written into the eeprom as the last byte of information. this is called the crc checksum. ? w hen the data is downloaded from the eeprom into the internal registers, a similar counter that sums all 1s from the values loaded into the registers is saved. this value is compared with the crc checksum from the previous upload operation. if the values match, the download operation was successful. if the values differ, the eeprom download operation failed, and the eeprom_crc fault flag is set (register 0xfe81, bit 5). to read the eeprom crc checksum value, execute the eeprom_crc_chksum command (register 0xd1). this command returns the crc checksum accumulated in the counter during the download operation. note that the crc checksum is an 8-bit cyclical accumulator that wraps around to 0 when 255 is reached.
data sheet ADP1047/adp1048 rev. 0 | page 41 of 84 software gui the software includes filter design and power supply pwm topology windows. the gui is also an information center, displaying the status of all readings, monitoring, and flags on the ADP1047 / adp1048 . a free software gui is available for programming and config- uring the ADP1047 / adp1048 . the gui is designed to be intuitive and dramatically reduces power supply design and development time. for more information about the gui, contact analog devices for the latest software and a user guide. 09696-044 figure 44. ADP1047 / adp1048 gui main window
ADP1047/adp1048 data sheet rev. 0 | page 42 of 84 standard pmbus commands supported by the ADP1047 / adp1048 table 15 lists the standard pmbus commands that are implemented on the ADP1047/ adp1048 . many of these commands are implemented in registers, which share the same hexadecimal value as the pmbus command code. table 15. standard pmbus commands command code command name 0x01 operation 0x02 on_off_config 0x03 clear_faults 0x10 write_protect 0x12 restore_default_all 0x15 store_user_all 0x16 restore_user_all 0x19 capability 0x20 vout_mode 0x21 vout_command 0x29 vout_scale_loop 0x2a vout_scale_monitor 0x35 vin_on 0x36 vin_off 0x40 vout_ov_fault_limit 0x41 vout_ov_fault_response 0x42 vout_ov_warn_limit 0x43 vout_uv_warn_limit 0x44 vout_uv_fault_limit 0x45 vout_uv_fault_response 0x50 ot_fault_response 0x55 vin_ov_fault_limit 0x56 vin_ov_fault_response 0x58 vin_uv_warn_limit 0x59 vin_uv_fault_limit 0x5a vin_uv_fault_response 0x5b iin_oc_fault_limit 0x5c iin_oc_fault_response 0x5d iin_oc_warn_limit 0x6b pin_op_warn_limit 0x78 status_byte 0x79 status_word 0x7a status_vout command code command name 0x7c status_input 0x7d status_temperature 0x88 read_vin 0x89 read_iin 0x8b read_vout 0x97 read_pin 0x98 pmbus_revision 0x99 mfr_id 0x9a mfr_model 0x9b mfr_revision 0xb0 eeprom_data_00 0xb1 eeprom_data_01 0xb2 eeprom_data_02 0xb3 eeprom_data_03 0xb4 eeprom_data_04 0xb5 eeprom_data_05 0xb6 eeprom_data_06 0xb7 eeprom_data_07 0xb8 eeprom_data_08 0xb9 eeprom_data_09 0xba eeprom_data_10 0xbb eeprom_data_11 0xbc eeprom_data_12 0xbd eeprom_data_13 0xbe eeprom_data_14 0xbf eeprom_data_15 0xd1 eeprom_crc_chksum 0xd2 eeprom_num_rd_bytes 0xd3 eeprom_addr_offset 0xd4 eeprom_page_erase 0xd5 eeprom_password 0xd6 trim_password 0xf1 eeprom_info
data sheet ADP1047/adp1048 rev. 0 | page 43 of 84 manufacturer-specific pmbus commands table 16 lists the manufacturer-specific pmbus commands that are implemented on the ADP1047 / adp1048 . these commands are implemented in registers, which share the same hexadecimal value as the pmbus command code. table 16. manufacturer-specific commands command code command name 0xfe00 cs_fast_ocp_response 0xfe01 ovp_fast_ovp_response 0xfe02 olp_response 0xfe03 vdd3p3_response 0xfe04 vcore_response 0xfe05 pgood_ac_ok_debounce_set 0xfe06 pson_set 0xfe07 flag_fault_id 0xfe08 softstart_flags_blank1 0xfe09 softstart_flags_blank2 0xfe0a pgood_flags_list 0xfe0b ac_ok_flags_list 0xfe0c pwm rising edge timing (pwm pin) 0xfe0d pwm rising edge setting (pwm pin) 0xfe0e pwm falling edge timing (pwm pin) 0xfe0f pwm falling edge setting (pwm pin) 0xfe10 pwm2 rising edge timing (pwm2 pin) 0xfe11 pwm2 rising edge setting (pwm2 pin) 0xfe12 pwm2 falling edge timing (pwm2 pin) 0xfe13 pwm2 falling edge setting (pwm2 pin) 0xfe14 pwm_set 0xfe15 pwm_limit 0xfe16 rtd adc offset trim setting (msb) 0xfe17 rtd adc offset trim setting (lsb) 0xfe18 rtd adc gain trim setting 0xfe19 ot_fault_limit 0xfe1a ot_warn_limit 0xfe1b switching frequency setting 0xfe1c low power switching frequency setting 0xfe1d frequency dithering set 0xfe1e frequency synchronization set 0xfe20 voltage loop filter gain 0xfe21 voltage loop filter zero 0xfe22 fast voltage loop filter gain 0xfe23 fast voltage loop filter zero 0xfe24 fast voltage loop enable 0xfe25 vac_threshold_set 0xfe26 vac_threshold_read 0xfe27 min_ac_period_set 0xfe28 max_ac_period_set 0xfe29 current loop filter gain for low line input 0xfe2a current loop filter zero for low line input 0xfe2b current loop filter gain for high line input 0xfe2c current loop filter zero for high line input 0xfe2d soft start set 0xfe2e inrush set command code command name 0xfe2f fast_ovp_fault_rise 0xfe30 fast_ovp_fault_fall 0xfe31 fast ovp debounce time setting 0xfe32 low power mode operation threshold 0xfe33 power metering offset trim for low line input 0xfe34 power metering gain trim for low line input 0xfe35 high line limit 0xfe36 low line limit 0xfe37 ilim_trim 0xfe38 voltage loop output 0xfe39 exponent 0xfe3a read update rate 0xfe3b vin scale monitor 0xfe3c iin_gsense 0xfe3d cs fast ocp blank 0xfe3e cs fast ocp setting 0xfe3f temperature hysteresis 0xfe40 vac adc gain trim 0xfe41 vfb adc gain trim 0xfe42 cs adc gain trim for 500 mv range 0xfe43 ibal gain ( adp1048 only) 0xfe44 smart vout low power threshold (p1) 0xfe45 smart vout high power threshold (p2) 0xfe46 smart vout low line (vol1) 0xfe47 smart vout low line (vol2) 0xfe48 smart vout high line (voh1) 0xfe49 smart vout high line (voh2) 0xfe4a smart vout upper limit (voh) 0xfe4b smart vout super high line 0xfe4c sync delay 0xfe4d smart_vout_super_high_line_hys 0xfe4e power_hys 0xfe4f advanced feature enable 0xfe50 vout_ov_fault_hys 0xfe51 vin_uv_fault_hys 0xfe53 vac adc offset trim 0xfe54 cs adc offset trim for 500 mv range 0xfe7e cs adc gain trim for high (750 mv) range 0xfe7f cs adc offset trim for high (750 mv) range 0xfe80 latched flag 0 0xfe81 latched flag 1 0xfe82 latched flag 2 0xfe84 pwm value 0xfe85 vac_line_period 0xfe86 read temperature adc 0xfe8e power metering offset trim for high line input
ADP1047/adp1048 data sheet rev. 0 | page 44 of 84 command code command name 0xfe8f power metering gain trim for high line input 0xfe90 current loop filter gain for low line input and light load 0xfe91 current loop filter zero for low line input and light load 0xfe92 current loop filter gain for high line input and light load 0xfe93 current loop filter zero for high line input and light load command code command name 0xfe94 smart vout power reading 0xfe95 ibal configuration ( adp1048 only) 0xfe96 debug flag 0 0xfe97 debug flag 1 0xfe98 debug flag 2 0xfe99 debug flag 3 0xfe9a debug flag 4 0xfe9b debug flag 5
data sheet ADP1047/adp1048 rev. 0 | page 45 of 84 detailed register descriptions operation register table 17. register 0x01operation bits bit name r/w description 7 enable r/w this bit determines the d evice response to the operation command. 0 = immediate off (no sequencing). 1 = device on. 6 rsvd r always reads as 0. [5:4] margin control r these bits set the output voltag e margin level and are hardcoded to a value of 00. [3:2] margin fault response r these bits set the device response to an outp ut ovp/uvp warning or fa ult after the output is margined. these bits are hardcoded to a value of 01. [1:0] rsvd r reserved. on_off_config register table 18. register 0x02on_off_config bits bit name r/w description [7:5] rsvd r reserved. 4 power-up control r/w set the device power-up response. 0 = device powers up when power is present. 1 = device powers up only when commanded by the control pin (pson) and the operation command. 3 command enable r/w control how the device responds to the operation command. 0 = ignore the operation command. 1 = the operation command must be set to 1 to enable the device (in addition to setting bit 2). 2 pin enable r/w control how the device responds to the value of the control pin (pson). 0 = ignore the control pin (pson). 1 = the control pin must be asserted to enable the device (in addition to setting bit 3). 1 control pin polarity r/w set the polarity of the control pin (pson). 0 = active low. 1 = active high. 0 power-down delay r actions to take on power-down. this bit always reads as 1 (turn off the output and stop energy transfer to the output as fast as possible). clear_faults command code 0x03, send byte, no data. this command clears all fault bits in all registers simultaneously. write_protect register table 19. register 0x10write_protect bits bit name r/w description 7 write protect 1 r/w setting this bit disables wr ites to all commands except for write_protect. 6 write protect 2 r/w setting this bit disables writes to all comma nds except for write_protect, operation, and eeprom_page_erase. 5 write protect 3 r/w setting this bit disables writes to all commands except for write_protect, operation, eeprom_page_erase, on_off_config, and vout_command. [4:0] rsvd r reserved. restore_default_all command code 0x12, send byte, no data. this command downloads the factory default parameters from eeprom into operating memory. store_user_all command code 0x15, send byte, no data. this command copies the entire contents of operating memory into eeprom (page 1 of the main bloc k).
ADP1047/adp1048 data sheet rev. 0 | page 46 of 84 restore_user_all command code 0x16, send byte, no data. this command downloads the stored user settings from eeprom into operating memory. capability register this register allows host systems to determine the capabilities of the pmbus device. table 20. register 0x19capability bits bit name r/w description 7 packet error checking r always reads as 0. packet error checking (pec) is not supported. [6:5] maximum bus speed r return the device pmbus speed capability. these bits are hardcoded to a value of 01 (use the 400 khz maximum bus speed). 4 smbalert# r always reads as 0. smbalert# pin an d smbus alert response protocol not supported. [3:0] rsvd r reserved. vout_mode register this register sets and reads the format (linear, vid, direct) and exponents for vout related commands. table 21. register 0x20vout_mode bits bit name r/w description [7:5] mode r return the output voltage data format . this bit is hardcoded to use linear format. [4:3] rsvd r reserved. [2:0] exponent r/w specify the exponent (n) used in vout linear mode format (x = y 2 n ). the exponent is in twos complement format. vout_command register this register sets vout to the configured value. table 22. register 0x21vout_command bits bit name r/w description [15:12] rsvd r reserved. always reads as 0000. [11:0] mantissa r/w mantissa (y[11:0]) used in vout linear mode format (x = y 2 n ). vout_scale_loop register this register sets the k factor = vadc/vout. table 23. register 0x29vout_scale_loop bits bit name r/w description [15:11] exponent r/w write the exponent (n) in twos complement format for k = y 2 n . 10 rsvd r always reads as 0. [9:0] mantissa r/w mantissa (y[9:0]) used in k linear mode format (k = y 2 n ).
data sheet ADP1047/adp1048 rev. 0 | page 47 of 84 vout_scale_monitor register this register sets the kr factor = vout/vadc. table 24. register 0x2avout_scale_monitor bits bit name r/w description [15:14] rsvd r reserved. [13:11] exponent r/w write the exponent (n) in twos complement format for kr = y 2 n . 10 rsvd r always reads as 0. [9:0] mantissa r/w mantissa (y[9:0]) used in kr linear mode format (kr = y 2 n ). vin_on register this register sets the value of the input voltage to start power conversion. table 25. register 0x35vin_on bits bit name r/w description [15:11] exponent r return the exponent (n) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]). [10:8] high bits r/w mantissa high bits (y[10: 8]) used in vin linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]). vin_off register this register sets the value of the input voltage to stop power conversion. table 26. register 0x36vin_off bits bit name r/w description [15:11] exponent r return the exponent (n) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]). [10:8] high bits r/w mantissa high bits (y[10: 8]) used in vin linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]). vout_ov_fault_limit register this register sets the accurate overvoltage threshold measured at the pfc output that causes an overvoltage fault condition. table 27. register 0x40vout_ov_fault_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in vout linear mode format (x = y 2 n ). the exponent (n) is set in the vout_mode register (register 0x20, bits[2:0]). the exponent is in twos complement format. [10:8] high bits r/w mantissa high bits (y[10:8] ) used in vout linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vout linear mode format (x = y 2 n ). vout_ov_fault_response register this register instructs the device on actions to take due to an output overvoltage fault condition. table 28. register 0x41vout_ov_fault_response bits bit name r/w description [7:6] response r/w these bits determine the device response to an output overvoltage fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the time specified by delay time 1 (bits[2:0]). if the fault persists, retry the number of times spec ified by the retry setting (bits[5:3]). 1 0 shut down, disable the output, and retry the number of times specified by the retry setting (bits[5:3]). 1 1 disable the output and wait for the fault to clear. after the fault is cleared, reenable the output.
ADP1047/adp1048 data sheet rev. 0 | page 48 of 84 bits bit name r/w description [5:3] retry setting r/w number of retry attempts following a fault condit ion. if the fault persists after the programmed number of attempts, the output is disabled and remains off until the faul t is cleared. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. the time between restart attempts is specified by delay time 2 (bits[2:0]). bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w delay time 1 is the delay before the device disabl es the output after a fault condition is detected. delay time 2 is the time between restart attempts. bit 2 bit 1 bit 0 delay time 1 delay time 2 0 0 0 10 ms 252 ms 0 0 1 20 ms 558 ms 0 1 0 40 ms 924 ms 0 1 1 80 ms 1260 ms 1 0 0 160 ms 1596 ms 1 0 1 320 ms 1932 ms 1 1 0 640 ms 2268 ms 1 1 1 1280 ms 2604 ms vout_ov_warn_limit register this register sets the accurate overvoltage threshold measured at the pfc output that causes an overvoltage warning condition. table 29. register 0x42vout_ov_warn_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in vout linear mode format (x = y 2 n ). the exponent (n) is set in the vout_mode register (register 0x20, bits[2:0]). the exponent is in twos complement format. [10:8] high bits r/w mantissa high bits (y[10:8] ) used in vout linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vout linear mode format (x = y 2 n ). vout_uv_warn_limit register this register sets the undervoltage threshold measured at the pfc output that causes an undervoltage warning condition. table 30. register 0x43vout_uv_warn_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in vout linear mode format (x = y 2 n ). the exponent (n) is set in the vout_mode register (register 0x20, bits[2:0]). the exponent is in twos complement format. [10:8] high bits r/w mantissa high bits (y[10:8] ) used in vout linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vout linear mode format (x = y 2 n ). vout_uv_fault_limit register this register sets the undervoltage threshold measured at the pfc output that causes an undervoltage fault condition. table 31. register 0x44vout_uv_fault_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in vout linear mode format (x = y 2 n ). the exponent (n) is set in the vout_mode register (register 0x20, bits[2:0]). the exponent is in twos complement format. [10:8] high bits r/w mantissa high bits (y[10:8] ) used in vout linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vout linear mode format (x = y 2 n ).
data sheet ADP1047/adp1048 rev. 0 | page 49 of 84 vout_uv_fault_response register this register instructs the device on actions to take due to an output undervoltage fault condition. table 32. register 0x45vout_uv_fault_response bits bit name r/w description [7:6] response r/w these bits determine the device re sponse to an output underv oltage fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the time specified by delay time 1 (bits[2:0]). if the fault persists, retry the number of times spec ified by the retry setting (bits[5:3]). 1 0 shut down, disable the output, and retry the number of times specified by the retry setting (bits[5:3]). 1 1 disable the output and wait for the fault to clear. after the fault is cleared, reenable the output. [5:3] retry setting r/w number of retry attempts following a fault condit ion. if the fault persists after the programmed number of attempts, the output is disabled and remains off until the faul t is cleared. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. the time between restart attempts is specified by delay time 2 (bits[2:0]). bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w delay time 1 is the delay before the device disabl es the output after a fault condition is detected. delay time 2 is the time between restart attempts. bit 2 bit 1 bit 0 delay time 1 delay time 2 0 0 0 10 ms 252 ms 0 0 1 20 ms 558 ms 0 1 0 40 ms 924 ms 0 1 1 80 ms 1260 ms 1 0 0 160 ms 1596 ms 1 0 1 320 ms 1932 ms 1 1 0 640 ms 2268 ms 1 1 1 1280 ms 2604 ms ot_fault_response register this register instructs the device on actions to take due to an overtemperature fault condition. table 33. register 0x50ot_fault_response bits bit name r/w description [7:6] response r/w these bits determine the device response to an overtemperature fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the time specified by delay time 1 (bits[2:0]). if the fault persists, retry the number of times spec ified by the retry setting (bits[5:3]). 1 0 shut down, disable the output, and retry the number of times specified by the retry setting (bits[5:3]). 1 1 disable the output and wait for the fault to clear. after the fault is cleared, reenable the output.
ADP1047/adp1048 data sheet rev. 0 | page 50 of 84 bits bit name r/w description [5:3] retry setting r/w number of retry attempts following a fault condit ion. if the fault persists after the programmed number of attempts, the output is disabled and remains off until the faul t is cleared. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. the time between restart attempts is specified by delay time 2 (bits[2:0]). bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w delay time 1 is the delay before the device disabl es the output after a fault condition is detected. delay time 2 is the time between restart attempts. bit 2 bit 1 bit 0 delay time 1 delay time 2 0 0 0 10 ms 252 ms 0 0 1 20 ms 558 ms 0 1 0 40 ms 924 ms 0 1 1 80 ms 1260 ms 1 0 0 160 ms 1596 ms 1 0 1 320 ms 1932 ms 1 1 0 640 ms 2268 ms 1 1 1 1280 ms 2604 ms vin_ov_fault_limit register this register sets the overvoltage threshold measured at the pfc input that causes an overvoltage fault condition. table 34. register 0x55vin_ov_fault_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]). [10:8] high bits r/w mantissa high bits (y[10: 8]) used in vin linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]). vin_ov_fault_response register this register instructs the device on actions to take due to an input overvoltage fault condition. table 35. register 0x56vin_ov_fault_response bits bit name r/w description [7:6] response r/w these bits determine the device response to an input overvoltage fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the time specified by delay time 1 (bits[2:0]). if the fault persists, retry the number of times spec ified by the retry setting (bits[5:3]). 1 0 shut down, disable the output, and retry the number of times specified by the retry setting (bits[5:3]). 1 1 disable the output and wait for the fault to clear. after the fault is cleared, reenable the output.
data sheet ADP1047/adp1048 rev. 0 | page 51 of 84 bits bit name r/w description [5:3] retry setting r/w number of retry attempts following a fault condit ion. if the fault persists after the programmed number of attempts, the output is disabled and remains off until the faul t is cleared. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. the time between restart attempts is specified by delay time 2 (bits[2:0]). bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w delay time 1 is the delay before the device disabl es the output after a fault condition is detected. delay time 2 is the time between restart attempts. bit 2 bit 1 bit 0 delay time 1 delay time 2 0 0 0 10 ms 252 ms 0 0 1 20 ms 558 ms 0 1 0 40 ms 924 ms 0 1 1 80 ms 1260 ms 1 0 0 160 ms 1596 ms 1 0 1 320 ms 1932 ms 1 1 0 640 ms 2268 ms 1 1 1 1280 ms 2604 ms vin_uv_warn_limit register this register sets the undervoltage threshold measured at the pfc input that causes an undervoltage warning condition. table 36. register 0x58vin_uv_warn_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in vin linear mode format (x = y 2 n ). the exponent is set in the exponent register (register 0xfe39, bits[5:3]). [10:8] high bits r/w mantissa high bits (y[10: 8]) used in vin linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]). vin_uv_fault_limit register this register sets the undervoltage threshold measured at the pfc input that causes an undervoltage fault condition. table 37. register 0x59vin_uv_fault_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in vin linear mode format (x = y 2 n ). the exponent is set in the exponent register (register 0xfe39, bits[5:3]). [10:8] high bits r/w mantissa high bits (y[10: 8]) used in vin linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]).
ADP1047/adp1048 data sheet rev. 0 | page 52 of 84 vin_uv_fault_response register this register instructs the device on actions to take due to an input undervoltage fault condition. table 38. register 0x5avin_uv_fault_response bits bit name r/w description [7:6] response r/w these bits determine the device re sponse to an input underv oltage fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the time specified by delay time 1 (bits[2:0]). if the fault persists, retry the number of times spec ified by the retry setting (bits[5:3]). 1 0 shut down, disable the output, and retry the number of times specified by the retry setting (bits[5:3]). 1 1 disable the output and wait for the fault to clear. after the fault is cleared, reenable the output. [5:3] retry setting r/w number of retry attempts following a fault condit ion. if the fault persists after the programmed number of attempts, the output is disabled and remains off until the faul t is cleared. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. the time between restart attempts is specified by delay time 2 (bits[2:0]). bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w delay time 1 is the delay before the device disabl es the output after a fault condition is detected. delay time 2 is the time between restart attempts. bit 2 bit 1 bit 0 delay time 1 delay time 2 0 0 0 10 ms 252 ms 0 0 1 20 ms 558 ms 0 1 0 40 ms 924 ms 0 1 1 80 ms 1260 ms 1 0 0 160 ms 1596 ms 1 0 1 320 ms 1932 ms 1 1 0 640 ms 2268 ms 1 1 1 1280 ms 2604 ms iin_oc_fault_limit register this register sets the accurate overcurrent threshold measured at the pfc input that causes an overcurrent fault condition. table 39. register 0x5biin_oc_fault_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in current linear mode format (x = y 2 n ). the exponent is set in the exponent register (register 0xfe39, bits[10:6]). [10:8] high bits r/w mantissa high bits (y[10:8] ) used in current linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in current linear mode format (x = y 2 n ).
data sheet ADP1047/adp1048 rev. 0 | page 53 of 84 iin_oc_fault_response register this register instructs the device on actions to take due to an input overcurrent fault condition. table 40. register 0x5ciin_oc_fault_response bits bit name r/w description [7:6] response r/w these bits determine the device response to an input over current fault condition. bit 7 bit 6 response 0 0 do nothing. 0 1 continue operation for the time specified by delay time 1 (bits[2:0]). if the fault persists, retry the number of times spec ified by the retry setting (bits[5:3]). 1 0 shut down, disable the output, and retry the number of times specified by the retry setting (bits[5:3]). 1 1 disable the output and wait for the fault to clear. after the fault is cleared, reenable the output. [5:3] retry setting r/w number of retry attempts following a fault condit ion. if the fault persists after the programmed number of attempts, the output is disabled and remains off until the faul t is cleared. a fault condition can be cleared by a reset, a power-off/power-on sequence, or a loss of bias power. the time between restart attempts is specified by delay time 2 (bits[2:0]). bit 5 bit 4 bit 3 number of retries 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 infinite [2:0] delay times r/w delay time 1 is the delay before the device disabl es the output after a fault condition is detected. delay time 2 is the time between restart attempts. bit 2 bit 1 bit 0 delay time 1 delay time 2 0 0 0 10 ms 252 ms 0 0 1 20 ms 558 ms 0 1 0 40 ms 924 ms 0 1 1 80 ms 1260 ms 1 0 0 160 ms 1596 ms 1 0 1 320 ms 1932 ms 1 1 0 640 ms 2268 ms 1 1 1 1280 ms 2604 ms iin_oc_warn_limit register this register sets the accurate overcurrent threshold measured at the pfc input that causes an overcurrent warning condition. table 41. register 0x5diin_oc_warn_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in current linear mode format (x = y 2 n ). the exponent is set in the exponent register (register 0xfe39, bits[10:6]). [10:8] high bits r/w mantissa high bits (y[10:8] ) used in current linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in current linear mode format (x = y 2 n ).
ADP1047/adp1048 data sheet rev. 0 | page 54 of 84 pin_op_warn_limit register this register sets the upper input power (w) threshold that causes an input overpower warning condition. table 42. register 0x6bpin_op_warn_limit bits bit name r/w description [15:11] exponent r return the exponent (n) used in power linear mode format (x = y 2 n ). the exponent is set in the exponent register (register 0xfe39, bits[2:0]). [10:8] high bits r/w mantissa high bits (y[10:8] ) used in power linear mode format (x = y 2 n ). [7:0] low byte r/w mantissa low byte (y[7:0]) used in power linear mode format (x = y 2 n ). status_byte register this register returns the lower byte of the status_word register. a value of 1 in this register indicates that a fault has occu rred. table 43. register 0x78status_byte bits bit name r/w description 7 busy r 1 = device was busy and unable to respond. 6 pson_off r 1 = device is not providing power to the output. 5 vout_ov r 1 = output overvoltage fault. 4 iout_oc r 1 = output overcurrent fault. 3 vin_uv r 1 = input undervoltage fault. 2 temperature r 1 = temperature fault or warning. 1 cml r 1 = communications, memory, or logic fault. 0 none_of_the_ above r 1 = fault or warning not listed in bits[7:1]. status_word register a value of 1 in this register indicates that a fault has occurred. table 44. register 0x79status_word bits bit name r/w description 15 vout r 1 = output voltage fault or warning. 14 iout/pout r 1 = output current or output power fault or warning. 13 input r 1 = input voltage, input curren t, or input power fault or warning. 12 mfr r 1 = manufacturer-spe cific fault or warning. 11 power_good# r 1 = power_good is negated. 10 fans r 1 = fan or airflow fault or warning. 9 other r always reads as 0. 8 unknown r 1 = fault or warning not listed in bits[15:1]. 7 busy r 1 = device was busy and unable to respond. 6 pson_off r 1 = device is not providing power to the output. 5 vout_ov r 1 = output overvoltage fault. 4 iout_oc r 1 = output overcurrent fault. 3 vin_uv r 1 = input undervoltage fault. 2 temperature r 1 = temperature fault or warning. 1 cml r 1 = communications, memory, or logic fault. 0 none_of_the_ above r 1 = fault or warning not listed in bits[7:1].
data sheet ADP1047/adp1048 rev. 0 | page 55 of 84 status_vout register a value of 1 in this register indicates that a fault has occurred. table 45. register 0x7astatus_vout bits bit name r/w description 7 vout_ov_fault r 1 = output overvoltage fault. 6 vout_ov_warn r 1 = output overvoltage warning. 5 vout_uv_warn r 1 = outp ut undervoltage warning. 4 vout_uv_fault r 1 = outp ut undervoltage fault. status_input register a value of 1 in this register indicates that a fault has occurred. table 46. register 0x7cstatus_input bits bit name r/w description 7 vin_ov_fault r 1 = input overvoltage fault. 5 vin_uv_warn r 1 = input undervoltage warning. 4 vin_uv_fault r 1 = inp ut undervoltage fault. 3 vin_low r 1 = device is off due to insufficient input volt age; that is, input voltage is below the turn-off threshold. 2 iin_oc_fault r 1 = input overcurrent fault. 1 iin_oc_warn r 1 = input overcurrent warning. 0 pin_op_warn r 1 = input overpower warning. status_temperature register a value of 1 in this register indicates that a fault has occurred. table 47. register 0x7dstatus_temperature bits bit name r/w description 7 ot_fault r 1 = overtemperature fault. 6 ot_warn r 1 = overtemperature warning. [5:0] rsvd r reserved. read_vin register this register returns the input voltage (v) in vin linear mode format (x = y 2 n ). table 48. register 0x88read_vin bits bit name r/w description [15:11] exponent r return the exponent (n) used in vin linear mode format (x = y 2 n ). the exponent is set in the exponent register (register 0xfe39, bits[5:3]). [10:8] high bits r mantissa high bits (y[10:8] ) used in vin linear mode format (x = y 2 n ). [7:0] low byte r mantissa low byte (y[7:0]) used in vin linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[5:3]). read_iin register this register returns the input current (a) in current linear mode format (x = y 2 n ). table 49. register 0x89read_iin bits bit name r/w description [15:11] exponent r return the exponent (n) used in current linear mode format (x = y 2 n ). the exponent is set in the exponent register (register 0xfe39, bits[10:6]). [10:8] high bits r mantissa high bits (y[10:8]) used in current linear mode format (x = y 2 n ). [7:0] low byte r mantissa low byte (y[7:0]) used in current linear mode format (x = y 2 n ).
ADP1047/adp1048 data sheet rev. 0 | page 56 of 84 read_vout register this register returns the output voltage (v) in vin linear mode format (x = y 2 n ). table 50. register 0x8bread_vout bits bit name r/w description [15:11] exponent r return the exponent (n) used in vout linear mode format (x = y 2 n ). the exponent (n) is set in the vout_mode register (register 0x20, bits[2:0]). the exponent is in twos complement format. [10:8] high bits r mantissa high bits (y[10:8] ) used in vout linear mode format (x = y 2 n ). [7:0] low byte r mantissa low byte (y[7:0]) used in vout linear mode format (x = y 2 n ). read_pin register this register returns the input power (w) in power linear mode format (x = y 2 n ). table 51. register 0x97read_pin bits bit name r/w description [15:11] exponent r return the exponent (n) used in power linear mode format (x = y 2 n ). the exponent (n) is set in the exponent register (register 0xfe39, bits[2:0]). [10:8] high bits r mantissa high bits (y[10:8] ) used in power linear mode format (x = y 2 n ). [7:0] low byte r mantissa low byte (y[7:0]) used in power linear mode format (x = y 2 n ). pmbus_revision register table 52. register 0x98pmbus_revision bits bit name r/w description [7:0] revision r return the revision of pmbus that the device is compliant with. mfr_id register table 53. register 0x99mfr_id bits bit name r/w description [7:0] mfr_id r return the manufacturers id. mfr_model register table 54. register 0x9amfr_model bits bit name r/w description [7:0] model r return the manufacturers model number. mfr_revision register table 55. register 0x9bmfr_revision bits bit name r/w description [7:0] revision r return the manufacturers revision number. eeprom_data_00 through eeprom_data_15 commands code 0xb0 through code 0xbf, read/write block. the eeprom_ data_00 through eeprom_data_15 commands are used to read data from the eeprom and write data to the eeprom. eeprom_data_00 reads from and writes to page 0 of the eeprom main block; eeprom_data_01 reads from and writes to page 1 of the eeprom main block, and so on.
data sheet ADP1047/adp1048 rev. 0 | page 57 of 84 eeprom_crc_chksum register table 56. register 0xd1eeprom_crc_chksum bits bit name r/w description [7:0] crc checksum r return the crc checksum value from the eeprom download operation. eeprom_num_rd_bytes register table 57. register 0xd2eeprom_num_rd_bytes bits bit name r/w description [7:0] number of read bytes returned r/w these bits set the number of read bytes returned when using the eeprom_data_xx commands. eeprom_addr_offset register table 58. register 0xd3eeprom_addr_offset bits bit name r/w description [15:0] address offset r/w these bits set th e address offset of the current eeprom page. eeprom_page_erase register table 59. register 0xd4eeprom_page_erase bits bit name r/w description [7:0] page erase w perform a page erase on the selected eeprom page . (wait 35 ms after each page erase operation.) eeprom must first be unlocked. page 0 and page 1 erase are allowed only in manufacturing test mode. eeprom_password register table 60. register 0xd5eeprom_password bits bit name r/w description [7:0] eeprom password w write the password to this register to unlock eeprom and/or to change the eeprom password. trim_password register table 61. register 0xd6trim_password bits bit name r/w description [7:0] trim password w write the password to this register to unlock the trim registers for write access. write the trim password twice (default 0x00) to unlock the register; write any other value to exit. eeprom_info command code 0xf1, block read/write. this command reads the manufacturers data from the eeprom.
ADP1047/adp1048 data sheet rev. 0 | page 58 of 84 cs_fast_ocp_response register this register instructs the device on actions to take due to a fast overcurrent protection condition. table 62. register 0xfe00cs_fast_ocp_response bits bit name r/w description [7:6] response r/w these bits determine the device re sponse to a fast overcurrent protection condition. bit 7 bit 6 response 0 0 ignore (still terminate the pwm pulse). 0 1 allow the number of switching cycles specified in bits[5:4], then shut down and soft start (use the soft start delay time specified in register 0x5c, bits[2:0]). 1 0 allow the number of switching cycles spec ified in bits[5:4] (terminating the pwm pulse each time), then shut down and wait for the pson signal to soft start. 1 1 disable the pwm output after the number of switching cycles specified in bits[5:4] and wait for the flag to be cleared. [5:4] n-time r/w these bits determine the number of switching cycl es allowed before the device disables the pwm output after a fast overcurrent condition is detected. bit 5 bit 4 number of switching cycles 0 0 1 0 1 2 1 0 4 1 1 8 [3:0] rsvd r reserved. ovp_fast_ovp_response register this register instructs the device on actions to take due to a fast overvoltage fault condition. table 63. register 0xfe01ovp_fast_ovp_response bits bit name r/w description [7:6] response r/w these bits determine the devi ce response to a fast overvoltage condition. bit 7 bit 6 response 0 0 ignore (do nothing; pwm continues). 0 1 shut down and soft start. 1 0 shut down immediately and wait for the pson signal. 1 1 disable the pwm output until the unlatched flag is cleared. [5:0] rsvd r reserved. olp_response register this register instructs the device on actions to take due to an open-loop fault condition. table 64. register 0xfe02olp_response bits bit name r/w description [7:6] response r/w these bits determine the device response to an open-loop fault condition. bit 7 bit 6 response 0 0 ignore (do nothing; pwm continues). 0 1 shut down and soft start. 1 0 shut down immediately and wait for the pson signal. 1 1 disable the pwm output until the unlatched flag is cleared. [5:0] rsvd r reserved.
data sheet ADP1047/adp1048 rev. 0 | page 59 of 84 vdd3p3_response register this register instructs the device on actions to take due to a vdd overvoltage fault condition. table 65. register 0xfe03vdd3p3_response bits bit name r/w description 7 rsvd r reserved. 6 save first flag id to eeprom r/w 1 = save the first flag id to eeprom when the device shuts down. 0 = do not save the first flag id to eeprom when the device shuts down. [5:3] retry wait time r/w these bits determine the retry wait time before the next soft start. each lsb = 588 ms. 2 reload eeprom r/w 1 = reload the contents of eeprom. 0 = do not reload the contents of eeprom. 1 debounce time r/w 1 = 2.56 s. 0 = 660 s. 0 ignore vdd ov r/w 1 = ignore the vdd 3.3 v overvoltage fault. 0 = do not ignore the vdd 3.3 v overvoltage fault. vcore_response register this register instructs the device on actions to take due to a vcore overvoltage fault condition. table 66. register 0xfe04vcore_response bits bit name r/w description 7 rsvd r reserved. 6 save first flag id to eeprom r/w 1 = save the first flag id to eeprom when the device shuts down. 0 = do not save the first flag id to eeprom when the device shuts down. [5:3] retry wait time r/w these bits determine the retry wait time before the next soft start. each lsb = 588 ms. 2 reload eeprom r/w 1 = reload the contents of eeprom. 0 = do not reload the contents of eeprom. 1 debounce time r/w 1 = 2.56 s. 0 = 660 s. 0 ignore vcore ov r/w 1 = ignore the vcore overvoltage fault. 0 = do not ignore the vcore overvoltage fault. pgood_ac_ok_debounce_set register this register sets the debounce times for the pgood and ac_ok pins. table 67. register 0xfe05pgood_ac_ok_debounce_set bits bit name r/w description [7:6] debounce time, ac_ok pin (low to high) r/w debounce from low to high for the ac_ok pin. bit 7 bit 6 time 0 0 0 ms 0 1 200 ms 1 0 320 ms 1 1 600 ms [5:4] debounce time, ac_ok pin (high to low) r/w debounce from high to low for the ac_ok pin. bit 5 bit 4 time 0 0 0 ms 0 1 200 ms 1 0 320 ms 1 1 600 ms
ADP1047/adp1048 data sheet rev. 0 | page 60 of 84 bits bit name r/w description [3:2] debounce time, pgood pin (low to high) r/w debounce from low to high for the pgood pin. bit 3 bit 2 time 0 0 0 ms 0 1 200 ms 1 0 320 ms 1 1 600 ms [1:0] debounce time, pgood pin (high to low) r/w debounce from high to low for the pgood pin. bit 1 bit 0 time 0 0 0 ms 0 1 200 ms 1 0 320 ms 1 1 600 ms pson_set register this register sets the delay time for pson and psoff. table 68. register 0xfe06pson_set bits bit name r/w description [7:4] rsvd r reserved. [3:2] pson delay r/w these bits specify the time from when the pson signal is active to when soft start begins. bit 3 bit 2 delay time min typ max 0 0 0 ms 0 ms 0 ms 0 1 40 ms 50 ms 82 ms 1 0 209 ms 250 ms 252 ms 1 1 964 ms 1000 ms 1007 ms [1:0] psoff delay r/w these bits specify th e time from when the pson signal is cleared to when the device is turned off. bit 1 bit 0 delay time min typ max 0 0 0 ms 0 ms 0 ms 0 1 40 ms 50 ms 82 ms 1 0 209 ms 250 ms 252 ms 1 1 964 ms 1000 ms 1007 ms flag_fault_id register this register records the first fault id that caused the system to shut down. table 69. register 0xfe07flag_fault_id bits bit name r/w description [7:4] previous fault flag id r return the flag fault id value of th e fault that occurred just before the flag that caused the shutdown (identified in bits[3:0]). [3:0] fault flag id r return the flag fault id value of the fault that caused the shutdown. bit 3 bit 2 bit 1 bit 0 fault 0 0 0 1 vout_ov_fault 0 0 1 0 vout_uv_fault 0 0 1 1 ot_fault 0 1 0 0 vin_ov_fault 0 1 0 1 vin_uv_fault 0 1 1 0 iin_oc_fault 0 1 1 1 olp_fault 1 0 0 0 fast_ovp_fault 1 0 0 1 fast_ocp_fault 1 0 1 0 vdd_33v_ov_fault 1 0 1 1 vcore_25v_ov_fault
data sheet ADP1047/adp1048 rev. 0 | page 61 of 84 softstart_flags_blank1 register this register blanks the specified flags during soft start (1 = blank, 0 = dont blank). table 70. register 0xfe08softstart_flags_blank1 bits bit name r/w description 7 blank_fast_ovp r/w 1 = ignore fast ovp flag. 6 blank_olp r/w 1 = ignore olp flag. 5 blank_iin_oc r/w 1 = ignore iin_oc_fault flag. 4 blank_vin_off r/w 1 = ignore vin_off flag. 3 blank_vin_ov r/w 1 = ignore vin_ov flag. 2 blank_ot r/w 1 = ignore ot flag. 1 blank_vout_uv r/w 1 = ignore vout_uv flag. 0 blank_vout_ov r/w 1 = ignore vout_ov flag. softstart_flags_blank2 register this register blanks the specified flag during soft start (1 = blank, 0 = dont blank). table 71. register 0xfe09softstart_flags_blank2 bits bit name r/w description 0 blank_fast_ocp r/w 1 = ignore fast ocp flag. pgood_flags_list register this register specifies the flags that are checked to determine the pgood pin voltage (1 = ignore flag, 0 = check flag). table 72. register 0xfe0apgood_flags_list bits bit name r/w description 7 vout_uv_fault r/w 1 = ignore vout_uv_fault flag. 6 vout_ov_warn r/w 1 = ignore vout_ov_warn flag. 5 fast_ovp r/w 1 = ignore fast_ovp flag. 4 olp r/w 1 = ignore olp flag. 3 fast_ocp r/w 1 = ignore fast_ocp flag. 2 iin_oc_fault r/w 1 = ignore iin_oc_fault flag. 1 ot_fault r/w 1 = ignore ot_fault flag. 0 fast_loop r/w 1 = ignore fast_loop flag. ac_ok_flags_list register this register specifies the flags that are checked to determine the ac_ok pin voltage (1 = ignore flag, 0 = check flag). table 73. register 0xfe0bac_ok_flags_list bits bit name r/w description 7 vin_uv_fault r/w 1 = ignore vin_uv_fault flag. 6 vin_uv_warn r/w 1 = ignore vin_uv_warn flag. 5 iin_oc_fault r/w 1 = ignore iin_oc_fault flag. 4 iin_oc_warn r/w 1 = ignore iin_oc_warn flag. 3 fast_ocp r/w 1 = ignore fast_ocp flag. 2 ac_line_period r/w 1 = ignore ac_line_period flag. 1 brown_out r/w 1 = ignore brown_out flag. 0 inrush r/w 1 = ignore inrush flag.
ADP1047/adp1048 data sheet rev. 0 | page 62 of 84 pwm and pwm2 timing registers register 0xfe0c through register 0xfe13 configure the rising and falling edges of the pwm outputs. table 74. register 0xfe0cpwm ri sing edge timing (pwm pin) bits bit name r/w description [7:0] t 1 r/w this register contains the eight msbs of the 10-bit t 1 time. table 75. register 0xfe0dpwm ri sing edge setting (pwm pin) bits bit name r/w description [7:4] rsvd r reserved. [3:2] t 1 r/w these bits contain the two lsbs of the 10-bit t 1 time. this value is always used with the eight bits of register 0xfe0c, which contains the eight msbs of the t 1 time. 1 modulate enable r/w 1 = pwm modulation acts on the t 1 edge. 0 = no pwm modulation of the t 1 edge. 0 t 1 sign r/w 1 = positive sign. increase of pwm modulation moves t 1 right. 0 = negative sign. increase of pwm modulation moves t 1 left. table 76. register 0xfe0epwm fa lling edge timing (pwm pin) bits bit name r/w description [7:0] t 2 r/w this register contains the eight msbs of the 10-bit t 2 time. table 77. register 0xfe0fpwm fa lling edge setting (pwm pin) bits bit name r/w description [7:4] rsvd r reserved. [3:2] t 2 r/w these bits contain the two lsbs of the 10-bit t 2 time. this value is always used with the eight bits of register 0xfe0e, which contains the eight msbs of the t 2 time. 1 modulate enable r/w 1 = pwm modulation acts on the t 2 edge. 0 = no pwm modulation of the t 2 edge. 0 t 2 sign r/w 1 = positive sign. increase of pwm modulation moves t 2 right. 0 = negative sign. increase of pwm modulation moves t 2 left. table 78. register 0xfe10pwm2 ri sing edge timing (pwm2 pin) bits bit name r/w description [7:0] t 1 r/w this register contains the eight msbs of the 10-bit t 1 time. table 79. register 0xfe11pwm2 ri sing edge setting (pwm2 pin) bits bit name r/w description [7:4] rsvd r reserved. [3:2] t 1 r/w these bits contain the two lsbs of the 10-bit t 1 time. this value is always used with the eight bits of register 0xfe10, which contains the eight msbs of the t 1 time. 1 modulate enable r/w 1 = pwm modulation acts on the t 1 edge. 0 = no pwm modulation of the t 1 edge. 0 t 1 sign r/w 1 = positive sign. increase of pwm modulation moves t 1 right. 0 = negative sign. increase of pwm modulation moves t 1 left. table 80. register 0xfe12pwm2 fa lling edge timing (pwm2 pin) bits bit name r/w description [7:0] t 2 r/w this register contains the eight msbs of the 10-bit t 2 time.
data sheet ADP1047/adp1048 rev. 0 | page 63 of 84 table 81. register 0xfe13pwm2 fa lling edge setting (pwm2 pin) bits bit name r/w description [7:4] rsvd r reserved. [3:2] t 2 r/w these bits contain the two lsbs of the 10-bit t 2 time. this value is always used with the eight bits of register 0xfe12, which contains the eight msbs of the t 2 time. 1 modulate enable r/w 1 = pwm modulation acts on the t 2 edge. 0 = no pwm modulation of the t 2 edge. 0 t 2 sign r/w 1 = positive sign. increase of pwm modulation moves t 2 right. 0 = negative sign. increase of pwm modulation moves t 2 left. pwm_set register table 82. register 0xfe14pwm_set bits bit name r/w description [7:5] rsvd r reserved. 4 adp1048 operation r/w reserved for the adp1048 only. 1 = bridgeless pfc operation. 0 = interleaved pfc operation. 3 pwm resolution r/w 1 = 5 ns. 0 = 40 ns. 2 pwm enable r/w 1 = disable the pwm output. 0 = enable the pwm output. 1 pwm2 enable r/w 1 = disable the pwm2 output. 0 = enable the pwm2 output. 0 go button r/w the pwm settings are updated during the transition of this bit from low to high. pwm_limit register table 83. register 0xfe15pwm_limit bits bit name r/w description [7:4] limit minimum on time r/w these bits set the minimum on time for the pw m outputs in steps of 80 ns: 0000 = 0 ns and 1111 = 1200 ns. [3:0] limit minimum off time r/w these bits set the minimum off time for th e pwm outputs: 0000 = 40 ns, 0001 = 80 ns, 1111 = 1200 ns. rtd adc offset trim setting (msb) register this register must be unlocked for write access; see tabl e 61 . table 84. register 0xfe16rtd adc offset trim setting (msb) bits bit name r/w description [7:2] rsvd r/w reserved. 1 trim polarity r/w 1 = negative offset trim is introduced. 0 = positive offset trim is introduced. 0 rtd adc offset trim r/w this bit is the msb of the 9-bit value that sets the amount of offset trim applied to the rtd adc reading. the lsbs are specified in register 0xfe17. rtd adc offset trim setting (lsb) register this register must be unlocked for write access; see tabl e 61 . table 85. register 0xfe17rtd adc offset trim setting (lsb) bits bit name r/w description [7:0] rtd adc offset trim r/w these eight bits are the lsbs of the 9-bit value th at sets the amount of offset trim applied to the rtd adc reading. the msb is specified in register 0xfe16, bit 0.
ADP1047/adp1048 data sheet rev. 0 | page 64 of 84 rtd adc gain trim setting register this register must be unlocked for write access; see tabl e 61 . table 86. register 0xfe18rtd adc gain trim setting bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] rtd adc gain trim r/w this value sets the amount of gain trim that is applie d to the rtd sensing gain. ot_fault_limit register this register sets the overtemperature fault threshold. the debounce time of the overtemperature fault flag is 100 ms. table 87. register 0xfe19ot_fault_limit bits bit name r/w description [7:0] ot fault threshold r/w overtemperature fault threshold. this register, adding 0 as the msb, results in a 9-bit threshold value. this 9-bit value is compared to the nine msbs of the rtd adc reading. if the rtd adc reading is lower than the threshold set by thes e bits, the overtemperature fault flag is set. these eight bits provide 256 threshold settings from 0 mv to 800 mv (one lsb = 800 mv/256 = 3.125 mv). however, the lowest allowed value is 9.375 mv (0x03), and the highest allowed value is 781.25 mv (0xfa). bit 7 bit 6 bit 3 bit 2 bit 1 bit 0 otp threshold (mv) 0 0 0 0 1 1 9.375 0 0 0 1 0 0 12.5 0 0 0 1 0 1 15.875 1 1 1 0 0 1 778.125 1 1 1 0 1 0 781.25 ot_warn_limit register this register sets the overtemperature warning threshold. the debounce time of the overtemperature warning flag is 100 ms. table 88. register 0xfe1aot_warn_limit bits bit name r/w description [7:0] ot warning threshold r/w overtemperature warning threshold. this register, adding 0 as the msb, results in a 9-bit threshold value. this 9-bit value is compared to the nine msbs of the rtd adc reading. if the rtd adc reading is lower than the thresh old set by these bits, the overtemperature warning flag is set. these eight bits provide 256 threshold settings from 0 mv to 800 mv (one lsb = 800 mv/256 = 3.125 mv). however, the lowest allowed value is 9.375 mv (0x03), and the highest allowed value is 781.25 mv (0xfa). bit 7 bit 6 bit 3 bit 2 bit 1 bit 0 otp threshold (mv) 0 0 0 0 1 1 9.375 0 0 0 1 0 0 12.5 0 0 0 1 0 1 15.875 1 1 1 0 0 1 778.125 1 1 1 0 1 0 781.25
data sheet ADP1047/adp1048 rev. 0 | page 65 of 84 switching frequency setting register table 89. register 0xfe1bswitching frequency setting bits bit name r/w description [7:6] rsvd r reserved. [5:0] switching frequency r/w this register sets the switching frequency of the pwm outputs. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frequency (khz) 0 0 0 0 0 0 30.05 0 0 0 0 0 1 32.55 0 0 0 0 1 0 35.51 0 0 0 0 1 1 39.06 0 0 0 1 0 0 43.40 0 0 0 1 0 1 48.83 0 0 0 1 1 0 52.06 0 0 0 1 1 1 55.80 0 0 1 0 0 0 60.10 0 0 1 0 0 1 65.10 0 0 1 0 1 0 71.02 0 0 1 0 1 1 78.13 0 0 1 1 0 0 86.81 0 0 1 1 0 1 97.66 0 0 1 1 1 0 100.81 0 0 1 1 1 1 104.17 0 1 0 0 0 0 107.76 0 1 0 0 0 1 111.61 0 1 0 0 1 0 115.74 0 1 0 0 1 1 120.19 0 1 0 1 0 0 125.00 0 1 0 1 0 1 130.21 0 1 0 1 1 0 135.87 0 1 0 1 1 1 142.05 0 1 1 0 0 0 148.81 0 1 1 0 0 1 156.25 0 1 1 0 1 0 164.47 0 1 1 0 1 1 173.61 0 1 1 1 0 0 183.82 0 1 1 1 0 1 195.31 0 1 1 1 1 0 198.41 0 1 1 1 1 1 201.61 1 0 0 0 0 0 204.92 1 0 0 0 0 1 208.33 1 0 0 0 1 0 211.86 1 0 0 0 1 1 215.52 1 0 0 1 0 0 219.30 1 0 0 1 0 1 223.21 1 0 0 1 1 0 227.27 1 0 0 1 1 1 231.48 1 0 1 0 0 0 235.85 1 0 1 0 0 1 240.38 1 0 1 0 1 0 245.10 1 0 1 0 1 1 250.00 1 0 1 1 0 0 255.10 1 0 1 1 0 1 260.42 1 0 1 1 1 0 265.96
ADP1047/adp1048 data sheet rev. 0 | page 66 of 84 bits bit name r/w description [5:0] switching frequency r/w bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frequency (khz) 1 0 1 1 1 1 271.74 1 1 0 0 0 0 277.78 1 1 0 0 0 1 284.09 1 1 0 0 1 0 290.70 1 1 0 0 1 1 297.62 1 1 0 1 0 0 304.88 1 1 0 1 0 1 312.50 1 1 0 1 1 0 320.51 1 1 0 1 1 1 328.95 1 1 1 0 0 0 337.84 1 1 1 0 0 1 347.22 1 1 1 0 1 0 357.14 1 1 1 0 1 1 367.65 1 1 1 1 0 0 378.79 1 1 1 1 0 1 390.63 1 1 1 1 1 0 403.23 1 1 1 1 1 1 403.23 low power switching frequency setting register this register sets the pfc switching frequency when the pfc is running under low power mode and the smart switching frequency operation is enabled. table 90. register 0xfe1clow power switching frequency setting bits bit name r/w description [7:6] rsvd r reserved. [5:0] switching frequency r/w this register sets the switching frequency when the power is lower than the low power threshold set in register 0xfe32 and the smart switching frequency is enabled. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frequency (khz) 0 0 0 0 0 0 30.05 0 0 0 0 0 1 32.55 0 0 0 0 1 0 35.51 0 0 0 0 1 1 39.06 0 0 0 1 0 0 43.40 0 0 0 1 0 1 48.83 0 0 0 1 1 0 52.06 0 0 0 1 1 1 55.80 0 0 1 0 0 0 60.10 0 0 1 0 0 1 65.10 0 0 1 0 1 0 71.02 0 0 1 0 1 1 78.13 0 0 1 1 0 0 86.81 0 0 1 1 0 1 97.66 0 0 1 1 1 0 100.81 0 0 1 1 1 1 104.17 0 1 0 0 0 0 107.76 0 1 0 0 0 1 111.61 0 1 0 0 1 0 115.74 0 1 0 0 1 1 120.19 0 1 0 1 0 0 125.00 0 1 0 1 0 1 130.21 0 1 0 1 1 0 135.87 0 1 0 1 1 1 142.05
data sheet ADP1047/adp1048 rev. 0 | page 67 of 84 bits bit name r/w description [5:0] switching frequency r/w bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frequency (khz) 0 1 1 0 0 0 148.81 0 1 1 0 0 1 156.25 0 1 1 0 1 0 164.47 0 1 1 0 1 1 173.61 0 1 1 1 0 0 183.82 0 1 1 1 0 1 195.31 0 1 1 1 1 0 198.41 0 1 1 1 1 1 201.61 1 0 0 0 0 0 204.92 1 0 0 0 0 1 208.33 1 0 0 0 1 0 211.86 1 0 0 0 1 1 215.52 1 0 0 1 0 0 219.30 1 0 0 1 0 1 223.21 1 0 0 1 1 0 227.27 1 0 0 1 1 1 231.48 1 0 1 0 0 0 235.85 1 0 1 0 0 1 240.38 1 0 1 0 1 0 245.10 1 0 1 0 1 1 250.00 1 0 1 1 0 0 255.10 1 0 1 1 0 1 260.42 1 0 1 1 1 0 265.96 1 0 1 1 1 1 271.74 1 1 0 0 0 0 277.78 1 1 0 0 0 1 284.09 1 1 0 0 1 0 290.70 1 1 0 0 1 1 297.62 1 1 0 1 0 0 304.88 1 1 0 1 0 1 312.50 1 1 0 1 1 0 320.51 1 1 0 1 1 1 328.95 1 1 1 0 0 0 337.84 1 1 1 0 0 1 347.22 1 1 1 0 1 0 357.14 1 1 1 0 1 1 367.65 1 1 1 1 0 0 378.79 1 1 1 1 0 1 390.63 1 1 1 1 1 0 403.23 1 1 1 1 1 1 403.23 frequency dithering set register table 91. register 0xfe1dfrequency dithering set bits bit name r/w description 7 rsvd r reserved. [6:0] dithering period r/w sets the pe riod for updating the switching frequency. each lsb corresponds to 40 s.
ADP1047/adp1048 data sheet rev. 0 | page 68 of 84 frequency synchronization set register table 92. register 0xfe1efrequency synchronization set bits bit name r/w description [7:2] rsvd r/w reserved. [1:0] frequency division r/w sets the frequency division between the switc hing frequency and the external sync clock (f sw /f sync_ext ). bit 1 bit 0 frequency division 0 0 1 0 1 1/2 1 0 1/3 1 1 1/4 voltage loop filter gain register table 93. register 0xfe20voltage loop filter gain bits bit name r/w description [7:0] voltage loop filter gain r/w determines the digital filter gain of the pfc voltage loop. voltage loop filter zero register table 94. register 0xfe21voltage loop filter zero bits bit name r/w description [7:0] voltage loop filter zero r/w determines the position of the digital filter zero of the pfc voltage loop. fast voltage loop filter gain register table 95. register 0xfe22fast voltage loop filter gain bits bit name r/w description [7:0] fast voltage loop filter gain r/w determines the digital filter ga in of the pfc fast voltage loop. fast voltage loop filter zero register table 96. register 0xfe23fast voltage loop filter zero bits bit name r/w description [7:0] fast voltage loop filter zero r/w determines the position of the digital filter zero of the pfc fast voltage loop. fast voltage loop enable register table 97. register 0xfe24fast voltage loop enable bits bit name r/w description 7 enable fast loop for line transient r/w enables fast loop mode immediately after the over shoot becomes larger than the regulation band plus 3%. 1 = enable fast loop mode. 0 = disable fast loop mode. [6:5] regulation band limit r/w sets the threshold of the regulation band limit for switching from the normal filter to the fast loop filter. bit 6 bit 5 threshold 0 0 1.5625% 0 1 3.125% 1 0 6.25% 1 1 12.5%
data sheet ADP1047/adp1048 rev. 0 | page 69 of 84 bits bit name r/w description [4:2] delay time r/w delay time before switching from the fast loop fi lter back to the normal filter after the output voltage is within the regulation band (bits[6:5]). bit 4 bit 3 bit 2 number of half ac line cycles 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 1 enable fast loop during soft start r/w enables the fast loop filter during soft start. 1 = fast loop filter is used during soft start. 0 = normal filter is used during soft start. 0 enable fast loop r/w enables the fast loop filter with a delay. the threshold is programmed in bits[6:5]. 1 = enable fast loop filter. 0 = disable fast loop filter. vac_threshold_set register this register sets the input voltage threshold for input ac line period measurement and zero-crossing detection. table 98. register 0xfe25vac_threshold_set bits bit name r/w description 7 enable automatic threshold r/w 1 = enable automatic threshold. 0 = disable automatic threshold. [6:0] threshold voltage r/w these bits set the threshold voltage to detect the ac line frequency and period if bit 7 is set to 0. vac_threshold_read register table 99. register 0xfe26vac_threshold_read bits bit name r/w description 7 rsvd r reserved. [6:0] vac average reading r return the reading of the threshold voltage to de tect the ac line frequency and period if the automatic threshold is enabled in register 0xfe25, bit 7. min_ac_period_set register table 100. register 0xfe27min_ac_period_set bits bit name r/w description [7:0] minimum ac line period r/w these bits set the minimum ac line period of the input voltage. each lsb corresponds to 163.84 s resolution. max_ac_period_set register table 101. register 0xfe28max_ac_period_set bits bit name r/w description [7:0] maximum ac line period r/w these bits set the maximum ac line period of th e input voltage. each lsb corresponds to 163.84 s resolution.
ADP1047/adp1048 data sheet rev. 0 | page 70 of 84 current loop filter gain for low line input register table 102. register 0xfe29current loop filter gain for low line input bits bit name r/w description [7:0] current loop filter gain for low line r/w these bits set the current loop digital filter gain of the pfc current loop under the low line input voltage. current loop filter zero for low line input register table 103. register 0xfe2acurrent lo op filter zero for low line input bits bit name r/w description [7:0] current loop filter zero for low line r/w these bits set the current loop digital filter zero of the pfc current loop under the low line input voltage. current loop filter gain fo r high line input register table 104. register 0xfe2bcurrent loop filter gain for high line input bits bit name r/w description [7:0] current loop filter gain for high line r/w these bits set the current loop digital filter ga in of the pfc current loop under the high line input voltage. current loop filter zero fo r high line input register table 105. register 0xfe2ccurrent loop filter zero for high line input bits bit name r/w description [7:0] current loop filter zero for high line r/w these bits set the current loop digital filter ze ro of the pfc current loop under the high line input voltage. soft start set register table 106. register 0xfe2dsoft start set bits bit name r/w description [7:6] rsvd r reserved. [5:3] soft start delay time r/w these bits set the delay time be tween the inrush signal and the beginning of the soft start. bit 5 bit 4 bit 3 number of full ac line cycles 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 [2:0] soft start time r/w these bits set the soft start time. bit 2 bit 1 bit 0 time 0 0 0 112 ms 0 0 1 168 ms 0 1 0 224 ms 0 1 1 280 ms 1 0 0 392 ms 1 0 1 504 ms 1 1 0 616 ms 1 1 1 728 ms
data sheet ADP1047/adp1048 rev. 0 | page 71 of 84 inrush set register table 107. register 0xfe2einrush set bits bit name r/w description [7:5] rsvd r reserved. [4:3] timer r/w these bits set the time r for the vin_low flag measurement. bit 4 bit 3 timer 0 0 quarter line cycle 0 1 half line cycle 1 0 2 ms 1 1 4 ms [2:0] inrush delay time r/w these bits set the inrush signal delay time after the brown_out flag goes low. bit 2 bit 1 bit 0 number of full ac line cycles 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 fast_ovp_fault_rise register table 108. register 0xfe2ffast_ovp_fault_rise bits bit name r/w description 7 rsvd r reserved. [6:0] fast ovp rise threshold r/w these bits set the rising thre shold for the analog comparator at the ovp pin input as follows : ovp threshold = ( code 0.492/128) + 1. this threshold is programmable from 1 v to 1.5 v. each lsb increments the threshold by 3.844 mv. a value of 0x00 corresponds to a 1 v threshold; a value of 0x3f correspond s to a 1.492 v threshold. fast_ovp_fault_fall register table 109. register 0xfe30fast_ovp_fault_fall bits bit name r/w description 7 rsvd r reserved. [6:0] fast ovp fall threshold r/w these bits set the falling thre shold for the analog comparator at the ovp pin input as follow s: ovp threshold = ( code 0.492/128) + 1. this threshold is programmable from 1 v to 1.5 v. each lsb increments the threshold by 3.844 mv. a value of 0x00 corresponds to a 1 v threshold; a value of 0x3f correspond s to a 1.492 v threshold. fast ovp debounce time setting register table 110. register 0xfe31fast ovp debounce time setting bits bit name r/w description [7:2] rsvd r reserved. [1:0] ovp debounce time r/w these bits set the fast ovp debounce time. bit 1 bit 0 time 0 0 120 ns 0 1 240 ns 1 0 480 ns 1 1 640 ns
ADP1047/adp1048 data sheet rev. 0 | page 72 of 84 low power mode operatio n threshold register table 111. register 0xfe32low power mode operation threshold bits bit name r/w description [7:0] low power threshold r/w these bits set the threshold value (p th ) for low power mode detection. when the input power is lower than this value, the pfc enters low power mode. power metering offset trim for low line input register table 112. register 0xfe33power metering offset trim for low line input bits bit name r/w description 7 offset trim polarity r/w 1 = negative offset trim is introduced. 0 = positive offset trim is introduced. [6:0] power meter offset trim r/w this value calibrates the power meter offset at the low line input voltage. each lsb corresponds to 0.0625/128 of the full input power. power metering gain trim for low line input register table 113. register 0xfe34power metering gain trim for low line input bits bit name r/w description 7 gain trim polarity r/w 1 = negative gain trim is introduced. 0 = positive gain trim is introduced. [6:0] power meter gain trim r/w this value calibrates the power meter gain at the low line input voltage. each lsb corresponds to 0.0625/128 of the input power. high line limit register table 114. register 0xfe35high line limit bits bit name r/w description [7:0] vac high line threshold r/w when the input voltage is higher than this value, the current loop filter for high line in put is used. low line limit register table 115. register 0xfe36low line limit bits bit name r/w description [7:0] vac low line threshold r/w when the input voltage is lower than this value, the current loop filter for low line input is used. ilim_trim register this register must be unlocked for write access; see tabl e 61 . table 116. register 0xfe37ilim_trim bits bit name r/w description [7:5] rsvd r reserved. 4 trim current direction r/w 1 = source trim current (ilim + ilim_trim). 0 = sink trim current (ilim ? ilim_trim). [3:0] ilim trim r/w these bits set the trim current. each lsb corresponds to ilim/64. voltage loop output register table 117. register 0xfe38voltage loop output bits bit name r/w description [7:0] voltage loop output r return th e output of the voltage control loop.
data sheet ADP1047/adp1048 rev. 0 | page 73 of 84 exponent register this register reads and writes exponents (n) for pin, vin, and iin. table 118. register 0xfe39exponent bits bit name r/w description [15:11] rsvd r reserved. [10:6] input current exponent r/w sets the exponent for the input current. [5:3] input voltage exponent r/w sets the exponent for the input voltage. [2:0] input power exponent r/w sets the exponent for the input power. read update rate register table 119. register 0xfe3aread update rate bits bit name r/w description [7:3] rsvd r reserved. [2:0] averaging window r/w these bits set the averaging window for the power current and voltage readings; rms values from one half ac line cycle are averaged over the programmed number of half ac line cycles. bit 2 bit 1 bit 0 number of half ac line cycles 0 0 0 0 0 0 1 16 0 1 0 64 0 1 1 128 1 0 0 512 1 0 1 1024 1 1 0 4096 1 1 1 8192 vin scale monitor register table 120. register 0xfe3bvin scale monitor bits bit name r/w description [15:14] rsvd r reserved. [13:11] exponent r/w write the exponent (n) in twos complement format (k vin = y 2 n ). 10 rsvd r reserved. [9:0] mantissa r/w mantissa (y[9:0]) used in k vin linear mode format (k vin = y 2 n ). iin_gsense register table 121. register 0xfe3ciin_gsense bits bit name r/w description [15:11] exponent r/w write the ex ponent (n) in twos complement format (iin_gsense = y 2 n ). 10 rsvd r reserved. [9:0] mantissa r/w mantissa (y[9:0]) used in iin linear mode format (iin_gsense = y 2 n ).
ADP1047/adp1048 data sheet rev. 0 | page 74 of 84 cs fast ocp blank register table 122. register 0xfe3dcs fast ocp blank bits bit name r/w description [7:5] rsvd r reserved. [4:3] cs ocp debounce time r/w these bits set the cs ocp debounce time. this valu e is the minimum time that the cs signal must be constantly above the ilim threshold (set in register 0xfe3e, bits[7:5]). when the cs ocp debounce time is exceeded, all pwm outputs are disabled for the remainder of the switching cycle. bit 4 bit 3 fast ocp debounce time 0 0 40 ns 0 1 80 ns 1 0 120 ns 1 1 240 ns [2:0] leading edge blanking time r/w these bits determine the leading edge blanking time. during this time, the ocp comparator output is ignored. bit 2 bit 1 bit 0 leading edge blanking time 0 0 0 40 ns 0 0 1 80 ns 0 1 0 120 ns 0 1 1 160 ns 1 0 0 200 ns 1 0 1 400 ns 1 1 0 600 ns 1 1 1 800 ns cs fast ocp setting register table 123. register 0xfe3ecs fast ocp setting bits bit name r/w description [7:5] ilim absolute value r/w these bits determine the ilim absolute value. bit 7 = 0 is positive sensing, and bit 7 = 1 is negative sensing. bit 7 bit 6 bit 5 ilim current value 0 0 0 20 a 0 0 1 40 a 0 1 0 60 a 0 1 1 80 a 1 0 0 60 a 1 0 1 80 a 1 1 0 100 a 1 1 1 120 a [4:2] rsvd r reserved. 1 cs_range_select r/w cs adc input range. 0 = 750 mv. 1 = 500 mv. 0 sel_resvi_ref r/w this bit sets the reference cu rrent for the cs+ and cs? common-mode level shift. 1 = select the res vi reference current (changing r res changes this current). 0 = select the band gap generated reference current. temperature hysteresis register table 124. register 0xfe3ftemperature hysteresis bits bit name r/w description [7:0] temperature hysteresis r/w these bits set the temperature (rtd) measurement hysteresis. the ot_fault flag is reset when the rtd adc value is higher than the temperatur e fault limit plus hysteresis. the ot_warn flag is reset when the rtd adc value is higher than the temperature warning limit plus hysteresis.
data sheet ADP1047/adp1048 rev. 0 | page 75 of 84 vac adc gain trim register this register must be unlocked for write access; see tabl e 61 . table 125. register 0xfe40vac adc gain trim bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] vac adc gain trim r/w this value calibrates the vac voltage sense gain. vfb adc gain trim register this register must be unlocked for write access; see tabl e 61 . table 126. register 0xfe41vfb adc gain trim bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] vfb adc gain trim r/w this value calibrates the output voltage sense gain. cs adc gain trim for 500 mv range register this register must be unlocked for write access; see tabl e 61 . table 127. register 0xfe42cs adc gain trim for 500 mv range bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] cs adc gain trim r/w this value calibrates the cs current sense gain. ibal gain register ( adp1048 only) table 128. register 0xfe43ibal gain ( adp1048 only) bits bit name r/w description 7 ibal enable r/w 1 = enable current balancing. 0 = disable current balancing and reset the ibal integrator. [6:0] ibal gain r/w the gain can be set from 0 to 127. smart vout low power th reshold (p1) register table 129. register 0xfe44smart vout low power threshold (p1) bits bit name r/w description [15:13] rsvd r reserved. [12:0] p1 r/w these bits set the threshold value for low power mode operation when the smart output voltage function is enabled. when the input powe r is lower than this value, the output voltage is vol1 for low line input and voh1 for high line input. smart vout high power th reshold (p2) register table 130. register 0xfe45smart vout high power threshold (p2) bits bit name r/w description [15:13] rsvd r reserved. [12:0] p2 r/w these bits set the threshold value for high power mode operation when the smart output voltage function is enabled. when the input power is higher than this value, the output voltage is vol2 for low line input and voh2 for high line input.
ADP1047/adp1048 data sheet rev. 0 | page 76 of 84 smart vout low line (vol1) register table 131. register 0xfe46smart vout low line (vol1) bits bit name r/w description [15:11] rsvd r reserved. [10:0] vol1 r/w these bits set the output voltage un der low power mode operation with low line input. smart vout low line (vol2) register table 132. register 0xfe47smart vout low line (vol2) bits bit name r/w description [15:11] rsvd r reserved. [10:0] vol2 r/w these bits set the output voltage unde r high power mode operation with low line input. smart vout high line (voh1) register table 133. register 0xfe48smart vout high line (voh1) bits bit name r/w description [15:11] rsvd r reserved. [10:0] voh1 r/w these bits set the output voltage unde r low power mode operation with high line input. smart vout high line (voh2) register table 134. register 0xfe49smart vout high line (voh2) bits bit name r/w description [15:11] rsvd r reserved. [10:0] voh2 r/w these bits set the output voltage unde r high power mode operation with high line input. smart vout upper limit (voh) register table 135. register 0xfe4asmart vout upper limit (voh) bits bit name r/w description [15:11] rsvd r reserved. [10:0] voh r/w these bits set the output voltage when the vac input voltage is higher than the value set in register 0xfe4b. smart vout super high line register table 136. register 0xfe4bsmart vout super high line bits bit name r/w description [15:11] rsvd r reserved. [10:0] super high line voltage r/w these bits set the input voltage value as a super high line limit. sync delay register table 137. register 0xfe4csync delay bits bit name r/w description [15:0] t sync_delay r/w these bits set the additional delay between the external synchronization reference clock signal and the rising edge of pwm. each lsb corresponds to 80 ns resolution.
data sheet ADP1047/adp1048 rev. 0 | page 77 of 84 smart_vout_super_high_line_hys register table 138. register 0xfe4dsmart_vout_super_high_line_hys bits bit name r/w description [7:0] super high line voltage hysteresis r/w these bits set the voltage hysteresis of the supe r high line voltage for the smart output voltage function. the output voltage is voh2 if the inpu t voltage is lower than the super high line voltage minus the voltage hysteresis. power_hys register table 139. register 0xfe4epower_hys bits bit name r/w description [7:0] power hysteresis r/w these bits set the power hysteresis for low power mode operation. the pfc exits the low power mode if the input power is higher than the low power threshold plus the power hysteresis. advanced feature enable register table 140. register 0xfe4fadvanced feature enable bits bit name r/w description 7 rsvd r reserved. 6 enable current loop feedforward r/w 1 = current loop feedforward is enabled. 0 = current loop feedforward is disabled. 5 enable light load current loop filter r/w 1 = light load current loop filter is enabled. 0 = light load current loop filter is disabled. 4 enable phase shedding r/w 1 = phase shedding is enabled. 0 = phase shedding is disabled. this bit applies to the adp1048 only. 3 enable smart switching frequency r/w 1 = smart switching frequency is enabled. 0 = smart switching frequency is disabled. 2 enable smart output voltage r/w 1 = smart output voltage is enabled. 0 = smart output voltage is disabled. 1 enable pwm synchronization r/w 1 = pwm frequency synchronization is enabled. 0 = pwm frequency synchronization is disabled. 0 enable frequency dithering r/w 1 = frequency dithering is enabled. 0 = frequency dithering is disabled. vout_ov_fault_hys register table 141. register 0xfe50vout_ov_fault_hys bits bit name r/w description [7:0] vout ov fault hysteresis r/w this register determines the mantissa hysteres is for the vout_ov_fault_limit condition. this hysteresis applies only when the disable output option is selected as the vout_ov_fault_ response (register 0x41, bits[7:6]). the pfc ou tput is reenabled when the output voltage is lower than vout_ov_fault_li mit minus this hysteresis. vin_uv_fault_hys register table 142. register 0xfe51vin_uv_fault_hys bits bit name r/w description [7:0] vin uv fault hysteresis r/w this register determines the mantissa hysteres is for the vin_uv_fault_limit condition. this hysteresis applies only when the disable o utput option is selected as the vin_uv_fault_ response (register 0x5a, bits[7:6]). the pfc ou tput is reenabled when the input voltage is higher than vin_uv_fault_lim it plus this hysteresis.
ADP1047/adp1048 data sheet rev. 0 | page 78 of 84 vac adc offset trim register this register must be unlocked for write access; see tabl e 61 . table 143. register 0xfe53vac adc offset trim bits bit name r/w description [7:0] vac adc offset trim r/w this register calibrates the vac ad c offset (the offset is always subtracted from the adc output) . cs adc offset trim for 500 mv range register this register must be unlocked for write access; see tabl e 61 . table 144. register 0xfe54cs adc offset trim for 500 mv range bits bit name r/w description [7:0] cs adc offset trim r/w this register calibrates the cs current sense offset (the offset is always subtracted from the adc output). cs adc gain trim for high (750 mv) range register this register must be unlocked for write access; see tabl e 61 . table 145. register 0xfe7ecs adc gain trim for high (750 mv) range bits bit name r/w description 7 gain polarity r/w 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] cs adc gain trim r/w this register calibrates the cs current sense gain. cs adc offset trim for high (750 mv) range register this register must be unlocked for write access; see tabl e 61 . table 146. register 0xfe7fcs adc offset trim for high (750 mv) range bits bit name r/w description [7:0] cs adc offset trim r/w this register calibrates the cs current sense offset (the offset is always subtracted from the adc output). latched flag registers the bits in the latched flag registers remain set (latched) to allow users to detect an intermittent fault. reading a latched f lag register resets the flags in that register. table 147. register 0xfe80latched flag 0 bits bit name r/w description 7 max_modulation r 1 = maximum modulation limit is reached. 6 min_modulation r 1 = minimum modulation limit is reached. 5 olp r 1 = one of the two voltage dividers is probably disconnected or malfunctioning. 4 fast_ovp r 1 = the threshold set for the comparator on the ovp pin has been crossed. 3 ac_period r 1 = controller is not able to detect the ac line period; the maximum value of the period is used and this flag is set. 2 brown_out r 1 = vac is lower than the value stored in vin_on (register 0x35). 1 soft_start r 1 = system is in soft star t sequence; fast loop filter is in use. 0 inrush r 1 = inrush control relay is off.
data sheet ADP1047/adp1048 rev. 0 | page 79 of 84 table 148. register 0xfe81latched flag 1 bits bit name r/w description 7 rsvd r reserved. 6 eeprom_unlocked r 1 = eeprom is unlocked and its contents can be written. 5 eeprom_crc r 1 = downloaded eeprom contents are incorrect. 4 i2c_address r 1 = the resistor on the add pin has a value that can cause an error in the address assignment (the address falls too close to the threshold between two addresses). 3 low_line r 1 = input voltage is higher than the high line threshold. 2 fast_ocp r 1 = the threshold set for the comparator on the ilim pin has been crossed. 1 sync_lock r 1 = external synchronization frequency is locked. 0 ac_ok r this flag is a programmable combination of other internal flags and refers to the condition of the input voltage. a value of 1 means that the output of the ac_ok pin is low. table 149. register 0xfe82latched flag 2 bits bit name r/w description [7:6] rsvd r reserved. 5 low_power r 1 = input power has dropped below the threshold for low power mode operation. 4 fast_loop r 1 = fast loop compensation filter is in use. 3 vcore_ov r 1 = an overvoltage condition is present on the vcore rail. 2 vdd_3.3v_ov r 1 = an overvoltage condition is present on the vdd rail. 1 vdd_3.3v_uv r 1 = an undervoltage condition is present on the vdd rail. 0 rsvd r reserved. pwm value register table 150. register 0xfe84pwm value bits bit name r/w description [7:0] pwm value r return the eight msbs of the pwm value (10 bits). vac_line_period register table 151. register 0xfe85vac_line_period bits bit name r/w description [7:0] vac line period r return the measured period on the vac pin signal. each lsb corresponds to 163.84 s. read temperature adc register table 152. register 0xfe86read temperature adc bits bit name r/w description [15:0] rtd temperature r return the meas ured temperature in adc 12-bit format. power metering offset trim fo r high line input register table 153. register 0xfe8epower meteri ng offset trim for high line input bits bit name r/w description 7 offset trim polarity r/w 1 = negative offset trim is introduced. 0 = positive offset trim is introduced. [6:0] power meter offset trim r/w this value calibrates the power meter offset at the high line input voltage. each lsb corresponds to 0.0625/128 of the full input power.
ADP1047/adp1048 data sheet rev. 0 | page 80 of 84 power metering gain trim for high line input register table 154. register 0xfe8fpower metering gain trim for high line input bits bit name r/w description 7 gain trim polarity r/w 1 = negative gain trim is introduced. 0 = positive gain trim is introduced. [6:0] power meter gain trim r/w this value calibrates the power meter gain at th e high line input voltage. each lsb corresponds to 0.0625/128 of the input power. current loop filter gain for low li ne input and light load register table 155. register 0xfe90current loop filter gain for low line input and light load bits bit name r/w description [7:0] current loop filter gain for low line and light load r/w these bits set the current loop digital filter gain of the pfc current loop under the low line input voltage at a light load condition if bit 5 of register 0xfe4f is set to 1. current loop filter zero for low li ne input and light load register table 156. register 0xfe91current loop filter zero for low line input and light load bits bit name r/w description [7:0] current loop filter zero for low line and light load r/w these bits set the current loop digital filter ze ro of the pfc current loop under the low line input voltage at a light load condition if bit 5 of register 0xfe4f is set to 1. current loop filter gain for high line input and light load register table 157. register 0xfe92current loop filter gain for high line input and light load bits bit name r/w description [7:0] current loop filter gain for high line and light load r/w these bits set the current loop digital filter ga in of the pfc current loop under the high line input voltage at a light load condition if bit 5 of register 0xfe4f is set to 1. current loop filter zero for high line input and light load register table 158. register 0xfe93current loop filter zero for high line input and light load bits bit name r/w description [7:0] current loop filter zero for high line and light load r/w these bits set the current loop digital filter ze ro of the pfc current loop under the high line input voltage at a light load condition if bit 5 of register 0xfe4f is set to 1. smart vout power reading register table 159. register 0xfe94smart vout power reading bits bit name r/w description [15:0] power reading r return the average power reading fo r smart output voltage (averaged over 16 full line cycles).
data sheet ADP1047/adp1048 rev. 0 | page 81 of 84 ibal configuration register ( adp1048 only) table 160. register 0xfe95ibal configuration ( adp1048 only) bits bit name r/w description 7 ibal disconnect r/w 1 = disconnect the output of the current balance block from the pwm outputs. 0 = connect the output of the current balance block to the pwm outputs. 6 ibal at load transient r/w 0 = disable current balancing when the fast loop is triggered. 1 = enable current balancing when the fast loop is triggered. it is recommended that this bit be set to 0. [5:4] rsvd r reserved. 3 ibal at low power mode r/w 1 = disable current balancing under low power mode if the output of the current balancing block reaches the limit. 0 = enable current balancing under low power mode even if the output of the current balancing block reaches the limit. it is recommended that this bit be set to 1. [2:0] rsvd r reserved. debug flag registers table 161. register 0xfe96debug flag 0 bits bit name r/w description 7 ot_warn r 1 = measured temperature is above the value of ot_warn_limit. 6 ot_fault r 1 = measured temperature is above the value of ot_fault_limit. 5 temperature r 1 = temperature fault or warning. 4 unknown r 1 = fault or warning not li sted in register 0x79, bits[15:1]. 3 mfr_fault r 1 = manufacturer-specific fault or warnin g (register 0xfe80, register 0xfe81, register 0xfe82). 2 pson r 1 = pson signal (hardware or software) is inactive. 1 pgood r power good. this flag is a programmable combinat ion of other internal flags and refers to the condition of the output voltage. a value of 1 me ans that the output of the pgood pin is low. 0 ac_ok r this flag is a programmable combination of other internal flags and refers to the condition of the input voltage. a value of 1 means that the output of the ac_ok pin is low. table 162. register 0xfe97debug flag 1 bits bit name r/w description 7 eeprom_unlocked r 1 = eeprom is unlocked and its contents can be written. 6 eeprom_crc r 1 = downloaded eeprom contents are incorrect. 5 i2c_address r 1 = the resistor on the add pin has a value that can cause an error in the address assignment (the address falls too close to the threshold between two addresses). 4 fast_loop r 1 = fast loop compensation filter is in use. 3 max_modulation r 1 = maximum modulation limit is reached. 2 min_modulation r 1 = minimum modulation limit is reached. 1 soft_start r 1 = system is in soft star t sequence; fast loop filter is in use. 0 sync_lock r 1 = external synchronization frequency is locked. table 163. register 0xfe98debug flag 2 bits bit name r/w description 7 vin_uv r 1 = general input undervoltage fault (same as register 0x7c, bit 4). 6 vin_low r 1 = vac is lower than vin_off (registe r 0x36). this signal shuts down the power supply. 5 vin_uv_fault r 1 = input voltage on vac is smaller than the value in vin_uv_fault_limit (register 0x59). 4 vin_uv_warn r 1 = input voltage on vac is smaller than the value in vin_uv_warn_limit (register 0x58). 3 low_line r 1 = input voltage is higher than the high line threshold. 2 brown_out r 1 = vac is lower than the value stored in vin_on (register 0x35). 1 cml r 1 = communications, memory, or logic fault. 0 vdd_3.3v_ov r 1 = an overvoltage condition is present on the vdd rail.
ADP1047/adp1048 data sheet rev. 0 | page 82 of 84 table 164. register 0xfe99debug flag 3 bits bit name r/w description 7 vin_ov_fault r 1 = input voltage on vac is larger than the value in vin_ov_fault_limit (register 0x55). 6 vcore_ov r 1 = an overvoltage condition is present on the vcore rail. 5 pin_op_warn r 1 = input overpower warning. 4 ac_period r 1 = controller is not able to detect the ac line period; the maximum value of the period is used and this flag is set. 3 iin_oc_warn r 1 = input current measured on the cs adc is larger than the value in iin_oc_warn_limit (register 0x5d). 2 iin_oc_fault r 1 = input current measured on the cs adc is larger than the value in iin_oc_fault_limit (register 0x5b). 1 fast_ocp r 1 = the threshold set for the comparator on the ilim pin has been crossed. 0 input r 1 = input voltage, input curren t, or input power fault or warning. table 165. register 0xfe9adebug flag 4 bits bit name r/w description 7 olp r 1 = one of the two voltage dividers is probably disconnected or malfunctioning. 6 fast_ovp r 1 = the threshold set for the comparator on the ovp pin has been crossed. 5 vout_uv_fault r 1 = output voltage is belo w the vout_uv_fault_limit (register 0x44). 4 vout_uv_warn r 1 = output voltage is belo w the vout_uv_warn_limit (register 0x43). 3 vout_ov_warn r 1 = output voltage is abov e the vout_ov_warn_limit (register 0x42). 2 vout_ov_fault r 1 = output voltage is abov e the vout_ov_fault_limit (register 0x40). 1 vout_ov r general output overvoltage fault: this flag is a combination (or) of any output overvoltage flag (register 0x7a, bit 7 and register 0xfe80, bit 4 (fast_ovp)). 0 vout r 1 = any fault on output voltage (overvolta ge, undervoltage, fast ovp, or accurate ovp). table 166. register 0xfe9bdebug flag 5 bits bit name r/w description [7:3] rsvd r reserved. 2 low_power r 1 = input power has dropped below the threshold for low power mode operation. 1 vdd_3.3v_uv r 1 = an undervoltage condition is present on the vdd rail. 0 inrush r 1 = inrush control relay is off.
data sheet ADP1047/adp1048 rev. 0 | page 83 of 84 outline dimensions compliant to jedec standards mo-137-ae controlling dimensions are in i nches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 24 13 12 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 01-03-2008-a figure 45. 24-lead shrink small outline package [qsop] (rq-24) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option ADP1047arqz-r7 ?40c to +85c 24-lead shri nk small outline package [qsop] rq-24 adp1048arqz-r7 ?40c to +85c 24-lead shri nk small outline package [qsop] rq-24 ADP1047-300-evalz ADP1047 300 w evaluation board adp1048-600-evalz adp1048 600 w evaluation board ADP1047dc1-evalz ADP1047 daughter card adp1048dc1-evalz adp1048 daughter card adp-i2c-usb-z usb to i 2 c adapter 1 z = rohs compliant part.
ADP1047/adp1048 data sheet rev. 0 | page 84 of 84 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09696-0-9/11(0)

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